
Long Pham
Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763 |
| Total Applications | 3774 |
| Issued Applications | 3306 |
| Pending Applications | 160 |
| Abandoned Applications | 335 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4138884
[patent_doc_number] => 06060335
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-09
[patent_title] => 'Semiconductor light emitting device and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 9/020900
[patent_app_country] => US
[patent_app_date] => 1998-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 21
[patent_no_of_words] => 12589
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/060/06060335.pdf
[firstpage_image] =>[orig_patent_app_number] => 020900
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/020900 | Semiconductor light emitting device and method of manufacturing the same | Feb 8, 1998 | Issued |
Array
(
[id] => 3999408
[patent_doc_number] => 05950081
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-07
[patent_title] => 'Method of fabricating semiconductor'
[patent_app_type] => 1
[patent_app_number] => 9/010177
[patent_app_country] => US
[patent_app_date] => 1998-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 1465
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/950/05950081.pdf
[firstpage_image] =>[orig_patent_app_number] => 010177
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/010177 | Method of fabricating semiconductor | Jan 20, 1998 | Issued |
Array
(
[id] => 3910500
[patent_doc_number] => 06001676
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'Semiconductor integrated circuit apparatus and associated fabrication'
[patent_app_type] => 1
[patent_app_number] => 9/009273
[patent_app_country] => US
[patent_app_date] => 1998-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 10783
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 415
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/001/06001676.pdf
[firstpage_image] =>[orig_patent_app_number] => 009273
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/009273 | Semiconductor integrated circuit apparatus and associated fabrication | Jan 19, 1998 | Issued |
Array
(
[id] => 4023787
[patent_doc_number] => 05882965
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-16
[patent_title] => 'Process for manufacturing an integrated CMOS circuit'
[patent_app_type] => 1
[patent_app_number] => 8/983263
[patent_app_country] => US
[patent_app_date] => 1998-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 2914
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/882/05882965.pdf
[firstpage_image] =>[orig_patent_app_number] => 983263
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/983263 | Process for manufacturing an integrated CMOS circuit | Jan 8, 1998 | Issued |
Array
(
[id] => 4070226
[patent_doc_number] => 05970331
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-19
[patent_title] => 'Method of making a plug transistor'
[patent_app_type] => 1
[patent_app_number] => 9/003981
[patent_app_country] => US
[patent_app_date] => 1998-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 18
[patent_no_of_words] => 4595
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/970/05970331.pdf
[firstpage_image] =>[orig_patent_app_number] => 003981
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/003981 | Method of making a plug transistor | Jan 6, 1998 | Issued |
Array
(
[id] => 3968856
[patent_doc_number] => 05904520
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-18
[patent_title] => 'Method of fabricating a CMOS transistor'
[patent_app_type] => 1
[patent_app_number] => 9/002930
[patent_app_country] => US
[patent_app_date] => 1998-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2003
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 249
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/904/05904520.pdf
[firstpage_image] =>[orig_patent_app_number] => 002930
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/002930 | Method of fabricating a CMOS transistor | Jan 4, 1998 | Issued |
Array
(
[id] => 4131279
[patent_doc_number] => 06121100
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Method of fabricating a MOS transistor with a raised source/drain extension'
[patent_app_type] => 1
[patent_app_number] => 9/001337
[patent_app_country] => US
[patent_app_date] => 1997-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 5315
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/121/06121100.pdf
[firstpage_image] =>[orig_patent_app_number] => 001337
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/001337 | Method of fabricating a MOS transistor with a raised source/drain extension | Dec 30, 1997 | Issued |
Array
(
[id] => 3943386
[patent_doc_number] => 05976921
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Method for manufacturing electrostatic discharge protection (ESD) and BiCMOS'
[patent_app_type] => 1
[patent_app_number] => 8/997481
[patent_app_country] => US
[patent_app_date] => 1997-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 112
[patent_no_of_words] => 17765
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 411
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/976/05976921.pdf
[firstpage_image] =>[orig_patent_app_number] => 997481
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/997481 | Method for manufacturing electrostatic discharge protection (ESD) and BiCMOS | Dec 22, 1997 | Issued |
Array
(
[id] => 3937074
[patent_doc_number] => 05981321
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'Forming CMOS transistor using diffusion source and wet/dry oxidation'
[patent_app_type] => 1
[patent_app_number] => 8/996292
[patent_app_country] => US
[patent_app_date] => 1997-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 1719
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/981/05981321.pdf
[firstpage_image] =>[orig_patent_app_number] => 996292
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/996292 | Forming CMOS transistor using diffusion source and wet/dry oxidation | Dec 21, 1997 | Issued |
Array
(
[id] => 4221980
[patent_doc_number] => 06010926
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-04
[patent_title] => 'Method for forming multiple or modulated wells of semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/995872
[patent_app_country] => US
[patent_app_date] => 1997-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 2604
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/010/06010926.pdf
[firstpage_image] =>[orig_patent_app_number] => 995872
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/995872 | Method for forming multiple or modulated wells of semiconductor device | Dec 21, 1997 | Issued |
Array
(
[id] => 4141756
[patent_doc_number] => 06030875
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-29
[patent_title] => 'Method for making semiconductor device having nitrogen-rich active region-channel interface'
[patent_app_type] => 1
[patent_app_number] => 8/994182
[patent_app_country] => US
[patent_app_date] => 1997-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3977
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/030/06030875.pdf
[firstpage_image] =>[orig_patent_app_number] => 994182
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/994182 | Method for making semiconductor device having nitrogen-rich active region-channel interface | Dec 18, 1997 | Issued |
Array
(
[id] => 3937017
[patent_doc_number] => 05915186
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-22
[patent_title] => 'Method of manufacturing heterojunction bipolar device having Si.sub.1-x Ge.sub.x base'
[patent_app_type] => 1
[patent_app_number] => 8/993862
[patent_app_country] => US
[patent_app_date] => 1997-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 32
[patent_no_of_words] => 6778
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/915/05915186.pdf
[firstpage_image] =>[orig_patent_app_number] => 993862
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/993862 | Method of manufacturing heterojunction bipolar device having Si.sub.1-x Ge.sub.x base | Dec 17, 1997 | Issued |
Array
(
[id] => 4057784
[patent_doc_number] => 05909616
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-01
[patent_title] => 'Method of forming CMOS circuitry'
[patent_app_type] => 1
[patent_app_number] => 8/982781
[patent_app_country] => US
[patent_app_date] => 1997-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2773
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 250
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/909/05909616.pdf
[firstpage_image] =>[orig_patent_app_number] => 982781
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/982781 | Method of forming CMOS circuitry | Dec 1, 1997 | Issued |
Array
(
[id] => 4094287
[patent_doc_number] => 06096585
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-01
[patent_title] => 'Method of manufacturing thin film transistor'
[patent_app_type] => 1
[patent_app_number] => 8/980797
[patent_app_country] => US
[patent_app_date] => 1997-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 30
[patent_no_of_words] => 5564
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/096/06096585.pdf
[firstpage_image] =>[orig_patent_app_number] => 980797
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/980797 | Method of manufacturing thin film transistor | Nov 30, 1997 | Issued |
Array
(
[id] => 4050531
[patent_doc_number] => 05943577
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-24
[patent_title] => 'Method of making heterojunction bipolar structure having air and implanted isolations'
[patent_app_type] => 1
[patent_app_number] => 8/982309
[patent_app_country] => US
[patent_app_date] => 1997-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 34
[patent_no_of_words] => 6680
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/943/05943577.pdf
[firstpage_image] =>[orig_patent_app_number] => 982309
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/982309 | Method of making heterojunction bipolar structure having air and implanted isolations | Nov 30, 1997 | Issued |
Array
(
[id] => 4046391
[patent_doc_number] => 05869366
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'Method for forming voltage clamp having a breakdown voltage of 40 Vdc'
[patent_app_type] => 1
[patent_app_number] => 8/977360
[patent_app_country] => US
[patent_app_date] => 1997-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 3911
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 309
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/869/05869366.pdf
[firstpage_image] =>[orig_patent_app_number] => 977360
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/977360 | Method for forming voltage clamp having a breakdown voltage of 40 Vdc | Nov 23, 1997 | Issued |
Array
(
[id] => 4031190
[patent_doc_number] => 05856003
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-05
[patent_title] => 'Method for forming pseudo buried layer for sub-micron bipolar or BiCMOS device'
[patent_app_type] => 1
[patent_app_number] => 8/971669
[patent_app_country] => US
[patent_app_date] => 1997-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 17
[patent_no_of_words] => 4144
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/856/05856003.pdf
[firstpage_image] =>[orig_patent_app_number] => 971669
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/971669 | Method for forming pseudo buried layer for sub-micron bipolar or BiCMOS device | Nov 16, 1997 | Issued |
Array
(
[id] => 4291733
[patent_doc_number] => 06180442
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-30
[patent_title] => 'Bipolar transistor with an inhomogeneous emitter in a BICMOS integrated circuit method'
[patent_app_type] => 1
[patent_app_number] => 8/970246
[patent_app_country] => US
[patent_app_date] => 1997-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 17
[patent_no_of_words] => 3793
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 35
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/180/06180442.pdf
[firstpage_image] =>[orig_patent_app_number] => 970246
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/970246 | Bipolar transistor with an inhomogeneous emitter in a BICMOS integrated circuit method | Nov 12, 1997 | Issued |
Array
(
[id] => 4155554
[patent_doc_number] => 06156594
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-05
[patent_title] => 'Fabrication of bipolar/CMOS integrated circuits and of a capacitor'
[patent_app_type] => 1
[patent_app_number] => 8/970070
[patent_app_country] => US
[patent_app_date] => 1997-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 3721
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/156/06156594.pdf
[firstpage_image] =>[orig_patent_app_number] => 970070
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/970070 | Fabrication of bipolar/CMOS integrated circuits and of a capacitor | Nov 12, 1997 | Issued |
Array
(
[id] => 4102256
[patent_doc_number] => 06051460
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-18
[patent_title] => 'Preventing boron penetration through thin gate oxide of P-channel devices by doping polygate with silicon'
[patent_app_type] => 1
[patent_app_number] => 8/968121
[patent_app_country] => US
[patent_app_date] => 1997-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 14
[patent_no_of_words] => 3035
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 280
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/051/06051460.pdf
[firstpage_image] =>[orig_patent_app_number] => 968121
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/968121 | Preventing boron penetration through thin gate oxide of P-channel devices by doping polygate with silicon | Nov 11, 1997 | Issued |