Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
08/960533 SELF-ALIGNED PROCESS FOR FABRICATING A PASSIVATING LEDGE IN A HETEROJUNCTION BIPOLAR TRANSISTOR Oct 30, 1997 Abandoned
Array ( [id] => 4012388 [patent_doc_number] => 05880001 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Method for forming epitaxial pinched resistor having reduced conductive cross sectional area' [patent_app_type] => 1 [patent_app_number] => 8/956829 [patent_app_country] => US [patent_app_date] => 1997-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3822 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880001.pdf [firstpage_image] =>[orig_patent_app_number] => 956829 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/956829
Method for forming epitaxial pinched resistor having reduced conductive cross sectional area Oct 22, 1997 Issued
Array ( [id] => 4348905 [patent_doc_number] => 06214749 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Process for producing semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/949283 [patent_app_country] => US [patent_app_date] => 1997-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 57 [patent_no_of_words] => 12663 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214749.pdf [firstpage_image] =>[orig_patent_app_number] => 949283 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/949283
Process for producing semiconductor devices Oct 20, 1997 Issued
Array ( [id] => 1542603 [patent_doc_number] => 06372590 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Method for making transistor having reduced series resistance' [patent_app_type] => B1 [patent_app_number] => 08/950717 [patent_app_country] => US [patent_app_date] => 1997-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4027 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372590.pdf [firstpage_image] =>[orig_patent_app_number] => 08950717 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/950717
Method for making transistor having reduced series resistance Oct 14, 1997 Issued
Array ( [id] => 4062536 [patent_doc_number] => 05866440 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Method of making compound semiconductor light emitting device having evaporation preventing layer Al.sub.x Ga.sub.(1-x) N' [patent_app_type] => 1 [patent_app_number] => 8/950527 [patent_app_country] => US [patent_app_date] => 1997-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 5251 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/866/05866440.pdf [firstpage_image] =>[orig_patent_app_number] => 950527 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/950527
Method of making compound semiconductor light emitting device having evaporation preventing layer Al.sub.x Ga.sub.(1-x) N Oct 13, 1997 Issued
Array ( [id] => 3832341 [patent_doc_number] => 05814547 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Forming different depth trenches simultaneously by microloading effect' [patent_app_type] => 1 [patent_app_number] => 8/944573 [patent_app_country] => US [patent_app_date] => 1997-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 1420 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/814/05814547.pdf [firstpage_image] =>[orig_patent_app_number] => 944573 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/944573
Forming different depth trenches simultaneously by microloading effect Oct 5, 1997 Issued
Array ( [id] => 3944975 [patent_doc_number] => 05953584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Method of fabricating liquid crystal display device having alignment direction determined' [patent_app_type] => 1 [patent_app_number] => 8/942197 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 2799 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953584.pdf [firstpage_image] =>[orig_patent_app_number] => 942197 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/942197
Method of fabricating liquid crystal display device having alignment direction determined Sep 30, 1997 Issued
Array ( [id] => 4003832 [patent_doc_number] => 05960257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Method distributed feedback semiconductor laser for fabricating' [patent_app_type] => 1 [patent_app_number] => 8/933707 [patent_app_country] => US [patent_app_date] => 1997-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 8669 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960257.pdf [firstpage_image] =>[orig_patent_app_number] => 933707 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/933707
Method distributed feedback semiconductor laser for fabricating Sep 18, 1997 Issued
Array ( [id] => 4289863 [patent_doc_number] => 06235601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Method of manufacturing a self-aligned vertical bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/934301 [patent_app_country] => US [patent_app_date] => 1997-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 1981 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235601.pdf [firstpage_image] =>[orig_patent_app_number] => 934301 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/934301
Method of manufacturing a self-aligned vertical bipolar transistor Sep 18, 1997 Issued
Array ( [id] => 3941679 [patent_doc_number] => 05989968 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Method of making bipolar transistor having reduced resistance' [patent_app_type] => 1 [patent_app_number] => 8/932765 [patent_app_country] => US [patent_app_date] => 1997-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 6909 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/989/05989968.pdf [firstpage_image] =>[orig_patent_app_number] => 932765 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/932765
Method of making bipolar transistor having reduced resistance Sep 16, 1997 Issued
Array ( [id] => 3768093 [patent_doc_number] => 05773337 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Method for forming ultra-shallow junction of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/929061 [patent_app_country] => US [patent_app_date] => 1997-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1956 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/773/05773337.pdf [firstpage_image] =>[orig_patent_app_number] => 929061 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/929061
Method for forming ultra-shallow junction of semiconductor device Sep 14, 1997 Issued
Array ( [id] => 3910731 [patent_doc_number] => 06001692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Method of fabricating trench MOS' [patent_app_type] => 1 [patent_app_number] => 8/926027 [patent_app_country] => US [patent_app_date] => 1997-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 2867 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/001/06001692.pdf [firstpage_image] =>[orig_patent_app_number] => 926027 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/926027
Method of fabricating trench MOS Sep 8, 1997 Issued
Array ( [id] => 3994299 [patent_doc_number] => 05918130 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Transistor fabrication employing formation of silicide across source and drain regions prior to formation of the gate conductor' [patent_app_type] => 1 [patent_app_number] => 8/929197 [patent_app_country] => US [patent_app_date] => 1997-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 4608 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918130.pdf [firstpage_image] =>[orig_patent_app_number] => 929197 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/929197
Transistor fabrication employing formation of silicide across source and drain regions prior to formation of the gate conductor Sep 7, 1997 Issued
Array ( [id] => 3836525 [patent_doc_number] => 05846857 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'CMOS processing employing removable sidewall spacers for independently optimized N- and P-channel transistor performance' [patent_app_type] => 1 [patent_app_number] => 8/924637 [patent_app_country] => US [patent_app_date] => 1997-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4142 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 407 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/846/05846857.pdf [firstpage_image] =>[orig_patent_app_number] => 924637 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/924637
CMOS processing employing removable sidewall spacers for independently optimized N- and P-channel transistor performance Sep 4, 1997 Issued
Array ( [id] => 4029294 [patent_doc_number] => 05994175 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'High performance MOSFET with low resistance design' [patent_app_type] => 1 [patent_app_number] => 8/924781 [patent_app_country] => US [patent_app_date] => 1997-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4808 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994175.pdf [firstpage_image] =>[orig_patent_app_number] => 924781 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/924781
High performance MOSFET with low resistance design Sep 4, 1997 Issued
Array ( [id] => 3957052 [patent_doc_number] => 05930611 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Method for fabricating MIS device having GATE insulator of GaS or gallium sulfide' [patent_app_type] => 1 [patent_app_number] => 8/923599 [patent_app_country] => US [patent_app_date] => 1997-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3890 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930611.pdf [firstpage_image] =>[orig_patent_app_number] => 923599 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/923599
Method for fabricating MIS device having GATE insulator of GaS or gallium sulfide Sep 3, 1997 Issued
Array ( [id] => 4218759 [patent_doc_number] => 06040208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Angled ion implantation for selective doping' [patent_app_type] => 1 [patent_app_number] => 8/920535 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5783 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040208.pdf [firstpage_image] =>[orig_patent_app_number] => 920535 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/920535
Angled ion implantation for selective doping Aug 28, 1997 Issued
Array ( [id] => 3828238 [patent_doc_number] => 05739062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Method of making bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/917467 [patent_app_country] => US [patent_app_date] => 1997-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 51 [patent_no_of_words] => 6764 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/739/05739062.pdf [firstpage_image] =>[orig_patent_app_number] => 917467 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/917467
Method of making bipolar transistor Aug 25, 1997 Issued
Array ( [id] => 3873183 [patent_doc_number] => 05824589 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Method for forming bipolar transistor having a reduced base transit time' [patent_app_type] => 1 [patent_app_number] => 8/915729 [patent_app_country] => US [patent_app_date] => 1997-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3865 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/824/05824589.pdf [firstpage_image] =>[orig_patent_app_number] => 915729 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/915729
Method for forming bipolar transistor having a reduced base transit time Aug 20, 1997 Issued
Array ( [id] => 132824 [patent_doc_number] => 07701059 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-20 [patent_title] => 'Low resistance metal silicide local interconnects and a method of making' [patent_app_type] => utility [patent_app_number] => 08/915658 [patent_app_country] => US [patent_app_date] => 1997-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5665 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/701/07701059.pdf [firstpage_image] =>[orig_patent_app_number] => 08915658 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/915658
Low resistance metal silicide local interconnects and a method of making Aug 20, 1997 Issued
Menu