Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3768864 [patent_doc_number] => 05849622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-15 [patent_title] => 'Method of forming a source implant at a contact masking step of a process flow' [patent_app_type] => 1 [patent_app_number] => 8/812555 [patent_app_country] => US [patent_app_date] => 1997-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 7963 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/849/05849622.pdf [firstpage_image] =>[orig_patent_app_number] => 812555 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/812555
Method of forming a source implant at a contact masking step of a process flow Mar 6, 1997 Issued
Array ( [id] => 3757198 [patent_doc_number] => 05721165 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Method of forming CMOS circuitry' [patent_app_type] => 1 [patent_app_number] => 8/810416 [patent_app_country] => US [patent_app_date] => 1997-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2772 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721165.pdf [firstpage_image] =>[orig_patent_app_number] => 810416 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/810416
Method of forming CMOS circuitry Mar 3, 1997 Issued
Array ( [id] => 3894760 [patent_doc_number] => 05750443 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/793593 [patent_app_country] => US [patent_app_date] => 1997-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3572 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/750/05750443.pdf [firstpage_image] =>[orig_patent_app_number] => 793593 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/793593
Method of manufacturing semiconductor device Mar 2, 1997 Issued
Array ( [id] => 3884208 [patent_doc_number] => 05776792 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Method for forming semiconductor laser device' [patent_app_type] => 1 [patent_app_number] => 8/811439 [patent_app_country] => US [patent_app_date] => 1997-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 14531 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/776/05776792.pdf [firstpage_image] =>[orig_patent_app_number] => 811439 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/811439
Method for forming semiconductor laser device Mar 2, 1997 Issued
Array ( [id] => 3885144 [patent_doc_number] => 05723357 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Supplementary implantation method for fabricating twin gate CMOS' [patent_app_type] => 1 [patent_app_number] => 8/808259 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 2321 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/723/05723357.pdf [firstpage_image] =>[orig_patent_app_number] => 808259 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/808259
Supplementary implantation method for fabricating twin gate CMOS Feb 27, 1997 Issued
Array ( [id] => 4006391 [patent_doc_number] => 05888844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Method of etching semiconductor laser device having Al.sub.x Ga.sub.1-x As and Al.sub.v Ga.sub.1-(v+y) In.sub.y P compound' [patent_app_type] => 1 [patent_app_number] => 8/806909 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 3215 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/888/05888844.pdf [firstpage_image] =>[orig_patent_app_number] => 806909 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/806909
Method of etching semiconductor laser device having Al.sub.x Ga.sub.1-x As and Al.sub.v Ga.sub.1-(v+y) In.sub.y P compound Feb 25, 1997 Issued
Array ( [id] => 3942237 [patent_doc_number] => 05946575 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Method for manufacturing low breakdown voltage MOS and high breakdown voltage MOS' [patent_app_type] => 1 [patent_app_number] => 8/807852 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3341 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946575.pdf [firstpage_image] =>[orig_patent_app_number] => 807852 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/807852
Method for manufacturing low breakdown voltage MOS and high breakdown voltage MOS Feb 25, 1997 Issued
Array ( [id] => 3967043 [patent_doc_number] => 05956591 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Method of making NMOS and PMOS devices having LDD structures using separate drive-in steps' [patent_app_type] => 1 [patent_app_number] => 8/805539 [patent_app_country] => US [patent_app_date] => 1997-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 24 [patent_no_of_words] => 5875 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956591.pdf [firstpage_image] =>[orig_patent_app_number] => 805539 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/805539
Method of making NMOS and PMOS devices having LDD structures using separate drive-in steps Feb 24, 1997 Issued
Array ( [id] => 3815310 [patent_doc_number] => 05770493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Method of making NMOS and PMOS devices with simultaneously formed gates having different gate lengths' [patent_app_type] => 1 [patent_app_number] => 8/805538 [patent_app_country] => US [patent_app_date] => 1997-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 4588 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/770/05770493.pdf [firstpage_image] =>[orig_patent_app_number] => 805538 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/805538
Method of making NMOS and PMOS devices with simultaneously formed gates having different gate lengths Feb 24, 1997 Issued
Array ( [id] => 3797050 [patent_doc_number] => 05827761 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Method of making NMOS and devices with sequentially formed gates having different gate lengths' [patent_app_type] => 1 [patent_app_number] => 8/805537 [patent_app_country] => US [patent_app_date] => 1997-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4485 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/827/05827761.pdf [firstpage_image] =>[orig_patent_app_number] => 805537 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/805537
Method of making NMOS and devices with sequentially formed gates having different gate lengths Feb 24, 1997 Issued
Array ( [id] => 3910308 [patent_doc_number] => 06001664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Method for making closely-spaced VCSEL and photodetector on a substrate' [patent_app_type] => 1 [patent_app_number] => 8/803891 [patent_app_country] => US [patent_app_date] => 1997-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6006 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/001/06001664.pdf [firstpage_image] =>[orig_patent_app_number] => 803891 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/803891
Method for making closely-spaced VCSEL and photodetector on a substrate Feb 20, 1997 Issued
Array ( [id] => 3745213 [patent_doc_number] => 05716880 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Method for forming vertical polysilicon diode compatible with CMOS/BICMOS formation' [patent_app_type] => 1 [patent_app_number] => 8/803467 [patent_app_country] => US [patent_app_date] => 1997-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 6766 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/716/05716880.pdf [firstpage_image] =>[orig_patent_app_number] => 803467 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/803467
Method for forming vertical polysilicon diode compatible with CMOS/BICMOS formation Feb 19, 1997 Issued
Array ( [id] => 4037749 [patent_doc_number] => 05908307 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Fabrication method for reduced-dimension FET devices' [patent_app_type] => 1 [patent_app_number] => 8/792107 [patent_app_country] => US [patent_app_date] => 1997-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3773 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/908/05908307.pdf [firstpage_image] =>[orig_patent_app_number] => 792107 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/792107
Fabrication method for reduced-dimension FET devices Jan 30, 1997 Issued
Array ( [id] => 3867426 [patent_doc_number] => 05837574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Method of manufacturing a thin poly, capacitor coupled contactless imager with high resolution and wide dynamic range' [patent_app_type] => 1 [patent_app_number] => 8/789397 [patent_app_country] => US [patent_app_date] => 1997-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 2128 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/837/05837574.pdf [firstpage_image] =>[orig_patent_app_number] => 789397 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/789397
Method of manufacturing a thin poly, capacitor coupled contactless imager with high resolution and wide dynamic range Jan 28, 1997 Issued
Array ( [id] => 3791482 [patent_doc_number] => 05726071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Manufacturing method of CMOS transistor' [patent_app_type] => 1 [patent_app_number] => 8/789315 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 51 [patent_no_of_words] => 11757 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726071.pdf [firstpage_image] =>[orig_patent_app_number] => 789315 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/789315
Manufacturing method of CMOS transistor Jan 22, 1997 Issued
Array ( [id] => 3769929 [patent_doc_number] => 05756382 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Manufacturing method of CMOS transistor' [patent_app_type] => 1 [patent_app_number] => 8/784354 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 51 [patent_no_of_words] => 11757 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/756/05756382.pdf [firstpage_image] =>[orig_patent_app_number] => 784354 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/784354
Manufacturing method of CMOS transistor Jan 22, 1997 Issued
Array ( [id] => 3867638 [patent_doc_number] => 05837589 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Method for making heterojunction bipolar mixer circuitry' [patent_app_type] => 1 [patent_app_number] => 8/774237 [patent_app_country] => US [patent_app_date] => 1996-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2333 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/837/05837589.pdf [firstpage_image] =>[orig_patent_app_number] => 774237 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/774237
Method for making heterojunction bipolar mixer circuitry Dec 26, 1996 Issued
Array ( [id] => 4023559 [patent_doc_number] => 05882950 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Fabrication method for horizontal direction semiconductor PN junction array' [patent_app_type] => 1 [patent_app_number] => 8/773185 [patent_app_country] => US [patent_app_date] => 1996-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1805 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/882/05882950.pdf [firstpage_image] =>[orig_patent_app_number] => 773185 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/773185
Fabrication method for horizontal direction semiconductor PN junction array Dec 26, 1996 Issued
Array ( [id] => 3740449 [patent_doc_number] => 05786244 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Method for making GaAs-InGaAs high electron mobility transistor' [patent_app_type] => 1 [patent_app_number] => 8/770183 [patent_app_country] => US [patent_app_date] => 1996-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1849 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/786/05786244.pdf [firstpage_image] =>[orig_patent_app_number] => 770183 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/770183
Method for making GaAs-InGaAs high electron mobility transistor Dec 18, 1996 Issued
Array ( [id] => 4030887 [patent_doc_number] => 05963801 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Method of forming retrograde well structures and punch-through barriers using low energy implants' [patent_app_type] => 1 [patent_app_number] => 8/770109 [patent_app_country] => US [patent_app_date] => 1996-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4400 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963801.pdf [firstpage_image] =>[orig_patent_app_number] => 770109 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/770109
Method of forming retrograde well structures and punch-through barriers using low energy implants Dec 18, 1996 Issued
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