Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3815296 [patent_doc_number] => 05770492 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Self-aligned twin well process' [patent_app_type] => 1 [patent_app_number] => 8/768845 [patent_app_country] => US [patent_app_date] => 1996-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 3626 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/770/05770492.pdf [firstpage_image] =>[orig_patent_app_number] => 768845 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/768845
Self-aligned twin well process Dec 17, 1996 Issued
Array ( [id] => 3836698 [patent_doc_number] => 05846867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Method of producing Si-Ge base heterojunction bipolar device' [patent_app_type] => 1 [patent_app_number] => 8/768171 [patent_app_country] => US [patent_app_date] => 1996-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 29 [patent_no_of_words] => 9551 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/846/05846867.pdf [firstpage_image] =>[orig_patent_app_number] => 768171 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/768171
Method of producing Si-Ge base heterojunction bipolar device Dec 16, 1996 Issued
Array ( [id] => 4006378 [patent_doc_number] => 05888843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Method for making light-emitting diode having improved moisture resistance characteristics' [patent_app_type] => 1 [patent_app_number] => 8/766867 [patent_app_country] => US [patent_app_date] => 1996-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4101 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/888/05888843.pdf [firstpage_image] =>[orig_patent_app_number] => 766867 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/766867
Method for making light-emitting diode having improved moisture resistance characteristics Dec 12, 1996 Issued
Array ( [id] => 3791334 [patent_doc_number] => 05780325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Methods of making isolations including doped edge layer, for semiconductor-on-insulator substrates' [patent_app_type] => 1 [patent_app_number] => 8/763673 [patent_app_country] => US [patent_app_date] => 1996-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3506 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/780/05780325.pdf [firstpage_image] =>[orig_patent_app_number] => 763673 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/763673
Methods of making isolations including doped edge layer, for semiconductor-on-insulator substrates Dec 10, 1996 Issued
Array ( [id] => 3888754 [patent_doc_number] => 05834326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Process for producing a luminous element of group III nitride semi-conductor' [patent_app_type] => 1 [patent_app_number] => 8/763779 [patent_app_country] => US [patent_app_date] => 1996-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 9415 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/834/05834326.pdf [firstpage_image] =>[orig_patent_app_number] => 763779 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/763779
Process for producing a luminous element of group III nitride semi-conductor Dec 10, 1996 Issued
Array ( [id] => 3943668 [patent_doc_number] => 05976940 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Method of making plurality of bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 8/762779 [patent_app_country] => US [patent_app_date] => 1996-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 46 [patent_no_of_words] => 14834 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/976/05976940.pdf [firstpage_image] =>[orig_patent_app_number] => 762779 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/762779
Method of making plurality of bipolar transistors Dec 9, 1996 Issued
Array ( [id] => 3825553 [patent_doc_number] => 05783469 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Method for making nitrogenated gate structure for improved transistor performance' [patent_app_type] => 1 [patent_app_number] => 8/763240 [patent_app_country] => US [patent_app_date] => 1996-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3795 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/783/05783469.pdf [firstpage_image] =>[orig_patent_app_number] => 763240 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/763240
Method for making nitrogenated gate structure for improved transistor performance Dec 9, 1996 Issued
Array ( [id] => 3894506 [patent_doc_number] => 05750424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Method for fabricating a CMOS device' [patent_app_type] => 1 [patent_app_number] => 8/764662 [patent_app_country] => US [patent_app_date] => 1996-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 3271 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/750/05750424.pdf [firstpage_image] =>[orig_patent_app_number] => 764662 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/764662
Method for fabricating a CMOS device Dec 9, 1996 Issued
Array ( [id] => 3740479 [patent_doc_number] => 05786247 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Low voltage CMOS process with individually adjustable LDD spacers' [patent_app_type] => 1 [patent_app_number] => 8/762411 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4301 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/786/05786247.pdf [firstpage_image] =>[orig_patent_app_number] => 762411 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/762411
Low voltage CMOS process with individually adjustable LDD spacers Dec 8, 1996 Issued
Array ( [id] => 4129928 [patent_doc_number] => 06033946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Method for fabricating an isolated NMOS transistor on a digital BiCMOS process' [patent_app_type] => 1 [patent_app_number] => 8/761267 [patent_app_country] => US [patent_app_date] => 1996-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 2714 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/033/06033946.pdf [firstpage_image] =>[orig_patent_app_number] => 761267 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/761267
Method for fabricating an isolated NMOS transistor on a digital BiCMOS process Dec 5, 1996 Issued
Array ( [id] => 4012402 [patent_doc_number] => 05880002 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Method for making isolated vertical PNP transistor in a digital BiCMOS process' [patent_app_type] => 1 [patent_app_number] => 8/761293 [patent_app_country] => US [patent_app_date] => 1996-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3726 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880002.pdf [firstpage_image] =>[orig_patent_app_number] => 761293 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/761293
Method for making isolated vertical PNP transistor in a digital BiCMOS process Dec 5, 1996 Issued
Array ( [id] => 3885963 [patent_doc_number] => 05714410 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Method for fabricating CMOS analog semiconductor' [patent_app_type] => 1 [patent_app_number] => 8/759209 [patent_app_country] => US [patent_app_date] => 1996-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4088 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/714/05714410.pdf [firstpage_image] =>[orig_patent_app_number] => 759209 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/759209
Method for fabricating CMOS analog semiconductor Dec 4, 1996 Issued
Array ( [id] => 3877206 [patent_doc_number] => 05804476 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Method of forming BiCMOS devices having mosfet and bipolar sections therein' [patent_app_type] => 1 [patent_app_number] => 8/758848 [patent_app_country] => US [patent_app_date] => 1996-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 3628 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 368 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/804/05804476.pdf [firstpage_image] =>[orig_patent_app_number] => 758848 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/758848
Method of forming BiCMOS devices having mosfet and bipolar sections therein Dec 1, 1996 Issued
Array ( [id] => 4034720 [patent_doc_number] => 05856228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Manufacturing method for making bipolar device having double polysilicon structure' [patent_app_type] => 1 [patent_app_number] => 8/757335 [patent_app_country] => US [patent_app_date] => 1996-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 93 [patent_no_of_words] => 18685 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/856/05856228.pdf [firstpage_image] =>[orig_patent_app_number] => 757335 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/757335
Manufacturing method for making bipolar device having double polysilicon structure Nov 26, 1996 Issued
Array ( [id] => 3619976 [patent_doc_number] => 05688710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Method of fabricating a twin - well CMOS device' [patent_app_type] => 1 [patent_app_number] => 8/757179 [patent_app_country] => US [patent_app_date] => 1996-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 1803 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/688/05688710.pdf [firstpage_image] =>[orig_patent_app_number] => 757179 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/757179
Method of fabricating a twin - well CMOS device Nov 26, 1996 Issued
Array ( [id] => 3826087 [patent_doc_number] => 05759883 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Method for making semiconductor device capable of independently forming MOS transistors and bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/752931 [patent_app_country] => US [patent_app_date] => 1996-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 4629 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/759/05759883.pdf [firstpage_image] =>[orig_patent_app_number] => 752931 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/752931
Method for making semiconductor device capable of independently forming MOS transistors and bipolar transistor Nov 19, 1996 Issued
Array ( [id] => 3686744 [patent_doc_number] => 05696016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Process for manufacturing a CMOSFET intergrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/746765 [patent_app_country] => US [patent_app_date] => 1996-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2111 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696016.pdf [firstpage_image] =>[orig_patent_app_number] => 746765 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/746765
Process for manufacturing a CMOSFET intergrated circuit Nov 14, 1996 Issued
Array ( [id] => 3768078 [patent_doc_number] => 05773336 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Methods of forming semiconductor active regions having channel-stop isolation regions therein' [patent_app_type] => 1 [patent_app_number] => 8/748193 [patent_app_country] => US [patent_app_date] => 1996-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 2518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/773/05773336.pdf [firstpage_image] =>[orig_patent_app_number] => 748193 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/748193
Methods of forming semiconductor active regions having channel-stop isolation regions therein Nov 11, 1996 Issued
Array ( [id] => 4113684 [patent_doc_number] => 06046070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Method of post-processing solid-state imaging device' [patent_app_type] => 1 [patent_app_number] => 8/745664 [patent_app_country] => US [patent_app_date] => 1996-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2368 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046070.pdf [firstpage_image] =>[orig_patent_app_number] => 745664 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/745664
Method of post-processing solid-state imaging device Nov 7, 1996 Issued
Array ( [id] => 3815280 [patent_doc_number] => 05770491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Manufacturing process of a MOS semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/747715 [patent_app_country] => US [patent_app_date] => 1996-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 1720 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/770/05770491.pdf [firstpage_image] =>[orig_patent_app_number] => 747715 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/747715
Manufacturing process of a MOS semiconductor device Nov 7, 1996 Issued
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