Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3832327 [patent_doc_number] => 05814546 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Method for producing a bipolar semiconductor device having SiC-based epitaxial layer' [patent_app_type] => 1 [patent_app_number] => 8/742937 [patent_app_country] => US [patent_app_date] => 1996-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3669 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/814/05814546.pdf [firstpage_image] =>[orig_patent_app_number] => 742937 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/742937
Method for producing a bipolar semiconductor device having SiC-based epitaxial layer Oct 31, 1996 Issued
Array ( [id] => 3687443 [patent_doc_number] => 05691225 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Method for fabricating semiconductor device having CMOS structure' [patent_app_type] => 1 [patent_app_number] => 8/739781 [patent_app_country] => US [patent_app_date] => 1996-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 2773 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/691/05691225.pdf [firstpage_image] =>[orig_patent_app_number] => 739781 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/739781
Method for fabricating semiconductor device having CMOS structure Oct 29, 1996 Issued
Array ( [id] => 3723455 [patent_doc_number] => 05681765 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Process for fabricating single polysilicon high performance BICMOS' [patent_app_type] => 1 [patent_app_number] => 8/738569 [patent_app_country] => US [patent_app_date] => 1996-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 1580 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/681/05681765.pdf [firstpage_image] =>[orig_patent_app_number] => 738569 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/738569
Process for fabricating single polysilicon high performance BICMOS Oct 27, 1996 Issued
Array ( [id] => 3813577 [patent_doc_number] => 05789301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Method for reducing extrinsic base-collector capacitance' [patent_app_type] => 1 [patent_app_number] => 8/736648 [patent_app_country] => US [patent_app_date] => 1996-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 2178 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/789/05789301.pdf [firstpage_image] =>[orig_patent_app_number] => 736648 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/736648
Method for reducing extrinsic base-collector capacitance Oct 24, 1996 Issued
Array ( [id] => 4038844 [patent_doc_number] => 05926705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Method for manufacturing a semiconductor device with stabilization of a bipolar transistor and a schottky barrier diode' [patent_app_type] => 1 [patent_app_number] => 8/736037 [patent_app_country] => US [patent_app_date] => 1996-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 3921 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926705.pdf [firstpage_image] =>[orig_patent_app_number] => 736037 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/736037
Method for manufacturing a semiconductor device with stabilization of a bipolar transistor and a schottky barrier diode Oct 20, 1996 Issued
Array ( [id] => 3888832 [patent_doc_number] => 05834331 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Method for making III-Nitride laser and detection device' [patent_app_type] => 1 [patent_app_number] => 8/733271 [patent_app_country] => US [patent_app_date] => 1996-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3739 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/834/05834331.pdf [firstpage_image] =>[orig_patent_app_number] => 733271 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/733271
Method for making III-Nitride laser and detection device Oct 16, 1996 Issued
Array ( [id] => 3881534 [patent_doc_number] => 05798277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Method for fabricating heterojunction bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/729841 [patent_app_country] => US [patent_app_date] => 1996-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 3908 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/798/05798277.pdf [firstpage_image] =>[orig_patent_app_number] => 729841 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/729841
Method for fabricating heterojunction bipolar transistor Oct 14, 1996 Issued
Array ( [id] => 3660195 [patent_doc_number] => 05648287 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Method of salicidation for deep quarter micron LDD MOSFET devices' [patent_app_type] => 1 [patent_app_number] => 8/729995 [patent_app_country] => US [patent_app_date] => 1996-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4812 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/648/05648287.pdf [firstpage_image] =>[orig_patent_app_number] => 729995 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/729995
Method of salicidation for deep quarter micron LDD MOSFET devices Oct 10, 1996 Issued
Array ( [id] => 3769915 [patent_doc_number] => 05756381 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Method providing, an enriched source side extension and a lightly doped extension' [patent_app_type] => 1 [patent_app_number] => 8/728405 [patent_app_country] => US [patent_app_date] => 1996-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3307 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/756/05756381.pdf [firstpage_image] =>[orig_patent_app_number] => 728405 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/728405
Method providing, an enriched source side extension and a lightly doped extension Oct 8, 1996 Issued
Array ( [id] => 3693929 [patent_doc_number] => 05650341 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Process for fabricating CMOS Device' [patent_app_type] => 1 [patent_app_number] => 8/720881 [patent_app_country] => US [patent_app_date] => 1996-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4189 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/650/05650341.pdf [firstpage_image] =>[orig_patent_app_number] => 720881 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/720881
Process for fabricating CMOS Device Oct 2, 1996 Issued
Array ( [id] => 3627119 [patent_doc_number] => 05686340 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'Manufacturing method of CMOS transistor' [patent_app_type] => 1 [patent_app_number] => 8/723710 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 51 [patent_no_of_words] => 11756 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/686/05686340.pdf [firstpage_image] =>[orig_patent_app_number] => 723710 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/723710
Manufacturing method of CMOS transistor Sep 29, 1996 Issued
Array ( [id] => 3813359 [patent_doc_number] => 05789285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Manufacturing method for BIMOS' [patent_app_type] => 1 [patent_app_number] => 8/720011 [patent_app_country] => US [patent_app_date] => 1996-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3535 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/789/05789285.pdf [firstpage_image] =>[orig_patent_app_number] => 720011 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/720011
Manufacturing method for BIMOS Sep 26, 1996 Issued
Array ( [id] => 3855529 [patent_doc_number] => 05705408 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Method for forming semiconductor integrated circuit using monolayer epitaxial growth' [patent_app_type] => 1 [patent_app_number] => 8/720175 [patent_app_country] => US [patent_app_date] => 1996-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 26 [patent_no_of_words] => 6025 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/705/05705408.pdf [firstpage_image] =>[orig_patent_app_number] => 720175 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/720175
Method for forming semiconductor integrated circuit using monolayer epitaxial growth Sep 24, 1996 Issued
Array ( [id] => 4023772 [patent_doc_number] => 05882964 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Process for the production of an integrated CMOS circuit' [patent_app_type] => 1 [patent_app_number] => 8/719411 [patent_app_country] => US [patent_app_date] => 1996-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 6065 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/882/05882964.pdf [firstpage_image] =>[orig_patent_app_number] => 719411 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/719411
Process for the production of an integrated CMOS circuit Sep 23, 1996 Issued
Array ( [id] => 3745339 [patent_doc_number] => 05716887 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Method of manufacturing BiCMOS device' [patent_app_type] => 1 [patent_app_number] => 8/710111 [patent_app_country] => US [patent_app_date] => 1996-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 3296 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/716/05716887.pdf [firstpage_image] =>[orig_patent_app_number] => 710111 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/710111
Method of manufacturing BiCMOS device Sep 12, 1996 Issued
Array ( [id] => 3945236 [patent_doc_number] => 05953604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Methods for making compact P-channel/N-channel transistor structure' [patent_app_type] => 1 [patent_app_number] => 8/712923 [patent_app_country] => US [patent_app_date] => 1996-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 6157 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953604.pdf [firstpage_image] =>[orig_patent_app_number] => 712923 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/712923
Methods for making compact P-channel/N-channel transistor structure Sep 12, 1996 Issued
Array ( [id] => 3869618 [patent_doc_number] => 05763289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method for fabricating multi-layer polymer thin florelectro-optical device' [patent_app_type] => 1 [patent_app_number] => 8/711903 [patent_app_country] => US [patent_app_date] => 1996-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 911 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/763/05763289.pdf [firstpage_image] =>[orig_patent_app_number] => 711903 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/711903
Method for fabricating multi-layer polymer thin florelectro-optical device Sep 11, 1996 Issued
Array ( [id] => 3756976 [patent_doc_number] => 05721147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Methods of forming bipolar junction transistors' [patent_app_type] => 1 [patent_app_number] => 8/712289 [patent_app_country] => US [patent_app_date] => 1996-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3972 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721147.pdf [firstpage_image] =>[orig_patent_app_number] => 712289 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/712289
Methods of forming bipolar junction transistors Sep 10, 1996 Issued
Array ( [id] => 3815021 [patent_doc_number] => 05770472 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Method for making monolithically integrated signal processing circuit having active and passive components' [patent_app_type] => 1 [patent_app_number] => 8/709997 [patent_app_country] => US [patent_app_date] => 1996-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4690 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/770/05770472.pdf [firstpage_image] =>[orig_patent_app_number] => 709997 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/709997
Method for making monolithically integrated signal processing circuit having active and passive components Sep 8, 1996 Issued
Array ( [id] => 4042114 [patent_doc_number] => 05874327 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Fabricating a semiconductor device using precursor CMOS semiconductor substrate of a given configuration' [patent_app_type] => 1 [patent_app_number] => 8/711283 [patent_app_country] => US [patent_app_date] => 1996-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 6855 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/874/05874327.pdf [firstpage_image] =>[orig_patent_app_number] => 711283 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/711283
Fabricating a semiconductor device using precursor CMOS semiconductor substrate of a given configuration Sep 8, 1996 Issued
Menu