
Long Pham
Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763 |
| Total Applications | 3774 |
| Issued Applications | 3306 |
| Pending Applications | 160 |
| Abandoned Applications | 335 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3759821
[patent_doc_number] => 05851865
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-22
[patent_title] => 'Method of manufacturing semiconductor device having mask layer forming step for ion implantation'
[patent_app_type] => 1
[patent_app_number] => 8/707659
[patent_app_country] => US
[patent_app_date] => 1996-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 33
[patent_no_of_words] => 3779
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/851/05851865.pdf
[firstpage_image] =>[orig_patent_app_number] => 707659
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/707659 | Method of manufacturing semiconductor device having mask layer forming step for ion implantation | Sep 3, 1996 | Issued |
Array
(
[id] => 4102420
[patent_doc_number] => 06051471
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-18
[patent_title] => 'Method for making asymmetrical N-channel and symmetrical P-channel devices'
[patent_app_type] => 1
[patent_app_number] => 8/711957
[patent_app_country] => US
[patent_app_date] => 1996-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 18
[patent_no_of_words] => 5701
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/051/06051471.pdf
[firstpage_image] =>[orig_patent_app_number] => 711957
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/711957 | Method for making asymmetrical N-channel and symmetrical P-channel devices | Sep 2, 1996 | Issued |
Array
(
[id] => 3697124
[patent_doc_number] => 05677224
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-14
[patent_title] => 'Method of making asymmetrical N-channel and P-channel devices'
[patent_app_type] => 1
[patent_app_number] => 8/711381
[patent_app_country] => US
[patent_app_date] => 1996-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 21
[patent_no_of_words] => 6251
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 309
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/677/05677224.pdf
[firstpage_image] =>[orig_patent_app_number] => 711381
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/711381 | Method of making asymmetrical N-channel and P-channel devices | Sep 2, 1996 | Issued |
Array
(
[id] => 3740142
[patent_doc_number] => 05786222
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-28
[patent_title] => 'Method of manufacturing high performance bipolar transistors in a BiCMOS process'
[patent_app_type] => 1
[patent_app_number] => 8/655055
[patent_app_country] => US
[patent_app_date] => 1996-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 5716
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/786/05786222.pdf
[firstpage_image] =>[orig_patent_app_number] => 655055
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/655055 | Method of manufacturing high performance bipolar transistors in a BiCMOS process | Aug 29, 1996 | Issued |
Array
(
[id] => 3815267
[patent_doc_number] => 05770490
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-23
[patent_title] => 'Method for producing dual work function CMOS device'
[patent_app_type] => 1
[patent_app_number] => 8/705579
[patent_app_country] => US
[patent_app_date] => 1996-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2193
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/770/05770490.pdf
[firstpage_image] =>[orig_patent_app_number] => 705579
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/705579 | Method for producing dual work function CMOS device | Aug 28, 1996 | Issued |
Array
(
[id] => 4034536
[patent_doc_number] => 05856215
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-05
[patent_title] => 'Method of fabricating a CMOS transistor'
[patent_app_type] => 1
[patent_app_number] => 8/701585
[patent_app_country] => US
[patent_app_date] => 1996-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 1638
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/856/05856215.pdf
[firstpage_image] =>[orig_patent_app_number] => 701585
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/701585 | Method of fabricating a CMOS transistor | Aug 21, 1996 | Issued |
Array
(
[id] => 4099588
[patent_doc_number] => 06066511
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-23
[patent_title] => 'Manufacturing method for a solid state imaging device'
[patent_app_type] => 1
[patent_app_number] => 8/701223
[patent_app_country] => US
[patent_app_date] => 1996-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3365
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/066/06066511.pdf
[firstpage_image] =>[orig_patent_app_number] => 701223
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/701223 | Manufacturing method for a solid state imaging device | Aug 20, 1996 | Issued |
Array
(
[id] => 3869866
[patent_doc_number] => 05763302
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-09
[patent_title] => 'Self-aligned twin well process'
[patent_app_type] => 1
[patent_app_number] => 8/704472
[patent_app_country] => US
[patent_app_date] => 1996-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 17
[patent_no_of_words] => 3471
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/763/05763302.pdf
[firstpage_image] =>[orig_patent_app_number] => 704472
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/704472 | Self-aligned twin well process | Aug 19, 1996 | Issued |
Array
(
[id] => 3768070
[patent_doc_number] => 05773335
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-30
[patent_title] => 'Method for forming twin-tub wells in substrate'
[patent_app_type] => 1
[patent_app_number] => 8/700161
[patent_app_country] => US
[patent_app_date] => 1996-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 22
[patent_no_of_words] => 3076
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/773/05773335.pdf
[firstpage_image] =>[orig_patent_app_number] => 700161
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/700161 | Method for forming twin-tub wells in substrate | Aug 19, 1996 | Issued |
Array
(
[id] => 3804683
[patent_doc_number] => 05830799
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-03
[patent_title] => 'Method for forming embedded diffusion layers using an alignment mark'
[patent_app_type] => 1
[patent_app_number] => 8/700081
[patent_app_country] => US
[patent_app_date] => 1996-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 30
[patent_no_of_words] => 9383
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/830/05830799.pdf
[firstpage_image] =>[orig_patent_app_number] => 700081
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/700081 | Method for forming embedded diffusion layers using an alignment mark | Aug 19, 1996 | Issued |
Array
(
[id] => 4085412
[patent_doc_number] => 06017785
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-25
[patent_title] => 'Method for improving latch-up immunity and interwell isolation in a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/698675
[patent_app_country] => US
[patent_app_date] => 1996-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 8385
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/017/06017785.pdf
[firstpage_image] =>[orig_patent_app_number] => 698675
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/698675 | Method for improving latch-up immunity and interwell isolation in a semiconductor device | Aug 14, 1996 | Issued |
Array
(
[id] => 3860721
[patent_doc_number] => 05795801
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-18
[patent_title] => 'MethodS of fabricating profiled device wells for improved device isolation'
[patent_app_type] => 1
[patent_app_number] => 8/694641
[patent_app_country] => US
[patent_app_date] => 1996-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2720
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/795/05795801.pdf
[firstpage_image] =>[orig_patent_app_number] => 694641
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/694641 | MethodS of fabricating profiled device wells for improved device isolation | Aug 8, 1996 | Issued |
Array
(
[id] => 3686599
[patent_doc_number] => 05696006
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'Method of manufacturing Bi-MOS device'
[patent_app_type] => 1
[patent_app_number] => 8/691341
[patent_app_country] => US
[patent_app_date] => 1996-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 33
[patent_no_of_words] => 13334
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/696/05696006.pdf
[firstpage_image] =>[orig_patent_app_number] => 691341
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/691341 | Method of manufacturing Bi-MOS device | Aug 1, 1996 | Issued |
Array
(
[id] => 3885131
[patent_doc_number] => 05723356
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-03
[patent_title] => 'Fabrication method for semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/688117
[patent_app_country] => US
[patent_app_date] => 1996-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 5506
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 230
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/723/05723356.pdf
[firstpage_image] =>[orig_patent_app_number] => 688117
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/688117 | Fabrication method for semiconductor device | Jul 28, 1996 | Issued |
Array
(
[id] => 3694645
[patent_doc_number] => 05661067
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-26
[patent_title] => 'Method for forming twin well'
[patent_app_type] => 1
[patent_app_number] => 8/686767
[patent_app_country] => US
[patent_app_date] => 1996-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 21
[patent_no_of_words] => 3393
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/661/05661067.pdf
[firstpage_image] =>[orig_patent_app_number] => 686767
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/686767 | Method for forming twin well | Jul 25, 1996 | Issued |
Array
(
[id] => 3660186
[patent_doc_number] => 05656515
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-12
[patent_title] => 'Method of making high-speed double-heterostructure bipolar transistor devices'
[patent_app_type] => 1
[patent_app_number] => 8/683291
[patent_app_country] => US
[patent_app_date] => 1996-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3451
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/656/05656515.pdf
[firstpage_image] =>[orig_patent_app_number] => 683291
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/683291 | Method of making high-speed double-heterostructure bipolar transistor devices | Jul 17, 1996 | Issued |
Array
(
[id] => 3867084
[patent_doc_number] => 05837553
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-17
[patent_title] => 'Method of making high voltage, junction isolation semiconductor device having dual conductivity type buried regions'
[patent_app_type] => 1
[patent_app_number] => 8/683599
[patent_app_country] => US
[patent_app_date] => 1996-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 3275
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 258
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/837/05837553.pdf
[firstpage_image] =>[orig_patent_app_number] => 683599
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/683599 | Method of making high voltage, junction isolation semiconductor device having dual conductivity type buried regions | Jul 14, 1996 | Issued |
Array
(
[id] => 3781958
[patent_doc_number] => 05821148
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-13
[patent_title] => 'Method of fabricating a segmented emitter low noise transistor'
[patent_app_type] => 1
[patent_app_number] => 8/678971
[patent_app_country] => US
[patent_app_date] => 1996-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2776
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/821/05821148.pdf
[firstpage_image] =>[orig_patent_app_number] => 678971
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/678971 | Method of fabricating a segmented emitter low noise transistor | Jul 11, 1996 | Issued |
Array
(
[id] => 3633378
[patent_doc_number] => 05631173
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-20
[patent_title] => 'Method for forming collector up heterojunction bipolar transistor having insulative extrinsic emitter'
[patent_app_type] => 1
[patent_app_number] => 8/679545
[patent_app_country] => US
[patent_app_date] => 1996-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 3557
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/631/05631173.pdf
[firstpage_image] =>[orig_patent_app_number] => 679545
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/679545 | Method for forming collector up heterojunction bipolar transistor having insulative extrinsic emitter | Jul 11, 1996 | Issued |
Array
(
[id] => 3877354
[patent_doc_number] => 05804487
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Method of fabricating high .beta.HBT devices'
[patent_app_type] => 1
[patent_app_number] => 8/676697
[patent_app_country] => US
[patent_app_date] => 1996-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 2875
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/804/05804487.pdf
[firstpage_image] =>[orig_patent_app_number] => 676697
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/676697 | Method of fabricating high .beta.HBT devices | Jul 9, 1996 | Issued |