Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3742579 [patent_doc_number] => 05801071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Method for producing semiconductor laser diode' [patent_app_type] => 1 [patent_app_number] => 8/677271 [patent_app_country] => US [patent_app_date] => 1996-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4565 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801071.pdf [firstpage_image] =>[orig_patent_app_number] => 677271 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/677271
Method for producing semiconductor laser diode Jul 8, 1996 Issued
Array ( [id] => 3727886 [patent_doc_number] => 05652154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Method for manufacturing BiMOS device' [patent_app_type] => 1 [patent_app_number] => 8/679379 [patent_app_country] => US [patent_app_date] => 1996-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4037 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652154.pdf [firstpage_image] =>[orig_patent_app_number] => 679379 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/679379
Method for manufacturing BiMOS device Jul 7, 1996 Issued
Array ( [id] => 3723071 [patent_doc_number] => 05672548 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'Method for attaching heat sinks directly to chip carrier modules using flexible-epoxy' [patent_app_type] => 1 [patent_app_number] => 8/668312 [patent_app_country] => US [patent_app_date] => 1996-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3309 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/672/05672548.pdf [firstpage_image] =>[orig_patent_app_number] => 668312 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/668312
Method for attaching heat sinks directly to chip carrier modules using flexible-epoxy Jun 25, 1996 Issued
Array ( [id] => 3687423 [patent_doc_number] => 05691224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Method of making BiCMOS circuit' [patent_app_type] => 1 [patent_app_number] => 8/668655 [patent_app_country] => US [patent_app_date] => 1996-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 2916 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/691/05691224.pdf [firstpage_image] =>[orig_patent_app_number] => 668655 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/668655
Method of making BiCMOS circuit Jun 24, 1996 Issued
Array ( [id] => 3885744 [patent_doc_number] => 05714397 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Process for producing lateral bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/666101 [patent_app_country] => US [patent_app_date] => 1996-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2483 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 377 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/714/05714397.pdf [firstpage_image] =>[orig_patent_app_number] => 666101 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/666101
Process for producing lateral bipolar transistor Jun 18, 1996 Issued
Array ( [id] => 4030872 [patent_doc_number] => 05963800 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'CMOS integration process having vertical channel' [patent_app_type] => 1 [patent_app_number] => 8/668215 [patent_app_country] => US [patent_app_date] => 1996-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 251 [patent_no_of_words] => 15474 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963800.pdf [firstpage_image] =>[orig_patent_app_number] => 668215 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/668215
CMOS integration process having vertical channel Jun 16, 1996 Issued
Array ( [id] => 3705102 [patent_doc_number] => 05654211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Method for manufacturing ultra-high speed bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/664823 [patent_app_country] => US [patent_app_date] => 1996-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 3757 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654211.pdf [firstpage_image] =>[orig_patent_app_number] => 664823 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/664823
Method for manufacturing ultra-high speed bipolar transistor Jun 16, 1996 Issued
Array ( [id] => 3768262 [patent_doc_number] => 05773349 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Method for making ultrahigh speed bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/664861 [patent_app_country] => US [patent_app_date] => 1996-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3734 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/773/05773349.pdf [firstpage_image] =>[orig_patent_app_number] => 664861 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/664861
Method for making ultrahigh speed bipolar transistor Jun 16, 1996 Issued
Array ( [id] => 3768529 [patent_doc_number] => 05733791 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Methods for fabrication of bipolar device having high ratio of emitter to base area' [patent_app_type] => 1 [patent_app_number] => 8/662956 [patent_app_country] => US [patent_app_date] => 1996-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3897 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/733/05733791.pdf [firstpage_image] =>[orig_patent_app_number] => 662956 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/662956
Methods for fabrication of bipolar device having high ratio of emitter to base area Jun 12, 1996 Issued
Array ( [id] => 3877142 [patent_doc_number] => 05804471 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Method of fabricating thin film transistor' [patent_app_type] => 1 [patent_app_number] => 8/657109 [patent_app_country] => US [patent_app_date] => 1996-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4001 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/804/05804471.pdf [firstpage_image] =>[orig_patent_app_number] => 657109 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/657109
Method of fabricating thin film transistor Jun 2, 1996 Issued
Array ( [id] => 3619850 [patent_doc_number] => 05688701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Method of making semiconductor device having a plurality of impurity layers' [patent_app_type] => 1 [patent_app_number] => 8/657251 [patent_app_country] => US [patent_app_date] => 1996-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 5568 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/688/05688701.pdf [firstpage_image] =>[orig_patent_app_number] => 657251 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/657251
Method of making semiconductor device having a plurality of impurity layers Jun 2, 1996 Issued
Array ( [id] => 4011682 [patent_doc_number] => 05879954 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Radiation-hard isoplanar cryo-CMOS process suitable for sub-micron devices' [patent_app_type] => 1 [patent_app_number] => 8/655303 [patent_app_country] => US [patent_app_date] => 1996-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 4817 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/879/05879954.pdf [firstpage_image] =>[orig_patent_app_number] => 655303 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/655303
Radiation-hard isoplanar cryo-CMOS process suitable for sub-micron devices May 19, 1996 Issued
Array ( [id] => 4057411 [patent_doc_number] => 05895259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Polysilicon diffusion doping method employing a deposited doped oxide layer with a highly uniform thickness' [patent_app_type] => 1 [patent_app_number] => 8/647637 [patent_app_country] => US [patent_app_date] => 1996-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4379 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895259.pdf [firstpage_image] =>[orig_patent_app_number] => 647637 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/647637
Polysilicon diffusion doping method employing a deposited doped oxide layer with a highly uniform thickness May 14, 1996 Issued
Array ( [id] => 3785644 [patent_doc_number] => 05736417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Method of fabricating double photoresist layer self-aligned heterojunction bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/647609 [patent_app_country] => US [patent_app_date] => 1996-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2116 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/736/05736417.pdf [firstpage_image] =>[orig_patent_app_number] => 647609 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/647609
Method of fabricating double photoresist layer self-aligned heterojunction bipolar transistor May 12, 1996 Issued
Array ( [id] => 3620451 [patent_doc_number] => 05641697 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'Method of making a MOS device with an input protection circuit LP' [patent_app_type] => 1 [patent_app_number] => 8/644447 [patent_app_country] => US [patent_app_date] => 1996-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2691 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/641/05641697.pdf [firstpage_image] =>[orig_patent_app_number] => 644447 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/644447
Method of making a MOS device with an input protection circuit LP May 12, 1996 Issued
Array ( [id] => 3700095 [patent_doc_number] => 05646055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Method for making bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/641393 [patent_app_country] => US [patent_app_date] => 1996-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2943 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646055.pdf [firstpage_image] =>[orig_patent_app_number] => 641393 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/641393
Method for making bipolar transistor Apr 30, 1996 Issued
Array ( [id] => 3832016 [patent_doc_number] => 05712188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Fabrication method of polarization-controlled surface-emitting laser diode using tilted-cavity' [patent_app_type] => 1 [patent_app_number] => 8/641531 [patent_app_country] => US [patent_app_date] => 1996-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2197 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712188.pdf [firstpage_image] =>[orig_patent_app_number] => 641531 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/641531
Fabrication method of polarization-controlled surface-emitting laser diode using tilted-cavity Apr 30, 1996 Issued
Array ( [id] => 3791659 [patent_doc_number] => 05726084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Method for forming integrated circuit structure' [patent_app_type] => 1 [patent_app_number] => 8/637963 [patent_app_country] => US [patent_app_date] => 1996-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 27 [patent_no_of_words] => 6076 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726084.pdf [firstpage_image] =>[orig_patent_app_number] => 637963 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/637963
Method for forming integrated circuit structure Apr 24, 1996 Issued
Array ( [id] => 3722794 [patent_doc_number] => 05672528 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'Method for making semiconductor device having field limiting ring' [patent_app_type] => 1 [patent_app_number] => 8/635509 [patent_app_country] => US [patent_app_date] => 1996-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4258 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/672/05672528.pdf [firstpage_image] =>[orig_patent_app_number] => 635509 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/635509
Method for making semiconductor device having field limiting ring Apr 21, 1996 Issued
Array ( [id] => 3696883 [patent_doc_number] => 05677209 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Method for fabricating a vertical bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/634267 [patent_app_country] => US [patent_app_date] => 1996-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5314 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 393 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677209.pdf [firstpage_image] =>[orig_patent_app_number] => 634267 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/634267
Method for fabricating a vertical bipolar transistor Apr 17, 1996 Issued
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