Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3647107 [patent_doc_number] => 05683927 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Method of forming CMOS integrated circuitry' [patent_app_type] => 1 [patent_app_number] => 8/631249 [patent_app_country] => US [patent_app_date] => 1996-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2487 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/683/05683927.pdf [firstpage_image] =>[orig_patent_app_number] => 631249 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/631249
Method of forming CMOS integrated circuitry Apr 11, 1996 Issued
Array ( [id] => 3993234 [patent_doc_number] => 05985687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method for making cleaved facets for lasers fabricated with gallium nitride and other noncubic materials' [patent_app_type] => 1 [patent_app_number] => 8/630675 [patent_app_country] => US [patent_app_date] => 1996-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5206 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/985/05985687.pdf [firstpage_image] =>[orig_patent_app_number] => 630675 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/630675
Method for making cleaved facets for lasers fabricated with gallium nitride and other noncubic materials Apr 11, 1996 Issued
Array ( [id] => 3665388 [patent_doc_number] => 05599723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Method for manufacturing bipolar transistor having reduced base-collector parasitic capacitance' [patent_app_type] => 1 [patent_app_number] => 8/626441 [patent_app_country] => US [patent_app_date] => 1996-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 6034 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/599/05599723.pdf [firstpage_image] =>[orig_patent_app_number] => 626441 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/626441
Method for manufacturing bipolar transistor having reduced base-collector parasitic capacitance Apr 1, 1996 Issued
Array ( [id] => 3796863 [patent_doc_number] => 05827747 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation' [patent_app_type] => 1 [patent_app_number] => 8/623435 [patent_app_country] => US [patent_app_date] => 1996-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 53 [patent_no_of_words] => 13863 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/827/05827747.pdf [firstpage_image] =>[orig_patent_app_number] => 623435 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/623435
Method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation Mar 27, 1996 Issued
Array ( [id] => 3849351 [patent_doc_number] => 05766999 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Method for making self-aligned bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/623573 [patent_app_country] => US [patent_app_date] => 1996-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7985 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/766/05766999.pdf [firstpage_image] =>[orig_patent_app_number] => 623573 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/623573
Method for making self-aligned bipolar transistor Mar 27, 1996 Issued
Array ( [id] => 3626884 [patent_doc_number] => 05686324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'Process for forming LDD CMOS using large-tilt-angle ion implantation' [patent_app_type] => 1 [patent_app_number] => 8/625587 [patent_app_country] => US [patent_app_date] => 1996-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 5624 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/686/05686324.pdf [firstpage_image] =>[orig_patent_app_number] => 625587 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/625587
Process for forming LDD CMOS using large-tilt-angle ion implantation Mar 27, 1996 Issued
Array ( [id] => 3872772 [patent_doc_number] => 05824560 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Method of manufacturing a semiconductor device with BICMOS circuit' [patent_app_type] => 1 [patent_app_number] => 8/623383 [patent_app_country] => US [patent_app_date] => 1996-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4045 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/824/05824560.pdf [firstpage_image] =>[orig_patent_app_number] => 623383 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/623383
Method of manufacturing a semiconductor device with BICMOS circuit Mar 26, 1996 Issued
Array ( [id] => 3727102 [patent_doc_number] => 05670417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Method for fabricating self-aligned semiconductor component' [patent_app_type] => 1 [patent_app_number] => 8/622535 [patent_app_country] => US [patent_app_date] => 1996-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2917 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/670/05670417.pdf [firstpage_image] =>[orig_patent_app_number] => 622535 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/622535
Method for fabricating self-aligned semiconductor component Mar 24, 1996 Issued
Array ( [id] => 4129666 [patent_doc_number] => 06033929 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Method for making II-VI group compound semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/620275 [patent_app_country] => US [patent_app_date] => 1996-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 7209 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/033/06033929.pdf [firstpage_image] =>[orig_patent_app_number] => 620275 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/620275
Method for making II-VI group compound semiconductor device Mar 21, 1996 Issued
Array ( [id] => 3813185 [patent_doc_number] => 05789273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Method for fabricating compound semiconductor laser' [patent_app_type] => 1 [patent_app_number] => 8/619085 [patent_app_country] => US [patent_app_date] => 1996-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2842 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/789/05789273.pdf [firstpage_image] =>[orig_patent_app_number] => 619085 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/619085
Method for fabricating compound semiconductor laser Mar 20, 1996 Issued
08/616663 ELECTRONIC COMPONENT AND PROCESS FOR MAKING IT Mar 17, 1996 Abandoned
Array ( [id] => 3622766 [patent_doc_number] => 05612242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'Trench isolation method for CMOS transistor' [patent_app_type] => 1 [patent_app_number] => 8/613517 [patent_app_country] => US [patent_app_date] => 1996-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 1821 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/612/05612242.pdf [firstpage_image] =>[orig_patent_app_number] => 613517 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/613517
Trench isolation method for CMOS transistor Mar 10, 1996 Issued
Array ( [id] => 3633420 [patent_doc_number] => 05631176 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-20 [patent_title] => 'Method of making combined JFET & MOS transistor device' [patent_app_type] => 1 [patent_app_number] => 8/612337 [patent_app_country] => US [patent_app_date] => 1996-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2791 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/631/05631176.pdf [firstpage_image] =>[orig_patent_app_number] => 612337 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/612337
Method of making combined JFET & MOS transistor device Mar 5, 1996 Issued
Array ( [id] => 3624796 [patent_doc_number] => 05620907 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-15 [patent_title] => 'Method for making a heterojunction bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/610646 [patent_app_country] => US [patent_app_date] => 1996-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 4454 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/620/05620907.pdf [firstpage_image] =>[orig_patent_app_number] => 610646 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/610646
Method for making a heterojunction bipolar transistor Mar 3, 1996 Issued
Array ( [id] => 3966710 [patent_doc_number] => 05956568 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Methods of fabricating and contacting ultra-small semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/613795 [patent_app_country] => US [patent_app_date] => 1996-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2904 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956568.pdf [firstpage_image] =>[orig_patent_app_number] => 613795 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/613795
Methods of fabricating and contacting ultra-small semiconductor devices Feb 29, 1996 Issued
Array ( [id] => 3730768 [patent_doc_number] => 05665615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Method of making BiCMOS semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/600539 [patent_app_country] => US [patent_app_date] => 1996-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8812 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/665/05665615.pdf [firstpage_image] =>[orig_patent_app_number] => 600539 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/600539
Method of making BiCMOS semiconductor device Feb 12, 1996 Issued
08/597097 METHOD OF FORMING SINGLE-CRYSTALLINE THIN FILM BY BEAM IRRADIATOR Feb 6, 1996 Abandoned
08/593117 CLOSELY-SPACED VCSEL AND PHOTODETECTOR FOR APPLICATIONS REQUIRING THEIR INDEPENDENT OPERATION Jan 31, 1996 Abandoned
Array ( [id] => 3832117 [patent_doc_number] => 05814531 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Method for forming semiconductor laser emitting light from slant plane' [patent_app_type] => 1 [patent_app_number] => 8/593697 [patent_app_country] => US [patent_app_date] => 1996-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7155 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/814/05814531.pdf [firstpage_image] =>[orig_patent_app_number] => 593697 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/593697
Method for forming semiconductor laser emitting light from slant plane Jan 28, 1996 Issued
Array ( [id] => 4046732 [patent_doc_number] => 05869389 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Semiconductor processing method of providing a doped polysilicon layer' [patent_app_type] => 1 [patent_app_number] => 8/588573 [patent_app_country] => US [patent_app_date] => 1996-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2430 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/869/05869389.pdf [firstpage_image] =>[orig_patent_app_number] => 588573 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/588573
Semiconductor processing method of providing a doped polysilicon layer Jan 17, 1996 Issued
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