Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4269505 [patent_doc_number] => 06245604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Bipolar-CMOS (BiCMOS) process for fabricating integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/585453 [patent_app_country] => US [patent_app_date] => 1996-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3941 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/245/06245604.pdf [firstpage_image] =>[orig_patent_app_number] => 585453 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/585453
Bipolar-CMOS (BiCMOS) process for fabricating integrated circuits Jan 15, 1996 Issued
Array ( [id] => 3770015 [patent_doc_number] => 05756387 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Method for forming zener diode with high time stability and low noise' [patent_app_type] => 1 [patent_app_number] => 8/581493 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2135 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/756/05756387.pdf [firstpage_image] =>[orig_patent_app_number] => 581493 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/581493
Method for forming zener diode with high time stability and low noise Dec 28, 1995 Issued
Array ( [id] => 3723424 [patent_doc_number] => 05681763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Method for making bipolar transistors having indium doped base' [patent_app_type] => 1 [patent_app_number] => 8/581665 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1426 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/681/05681763.pdf [firstpage_image] =>[orig_patent_app_number] => 581665 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/581665
Method for making bipolar transistors having indium doped base Dec 28, 1995 Issued
Array ( [id] => 4234910 [patent_doc_number] => 06165826 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Transistor with low resistance tip and method of fabrication in a CMOS process' [patent_app_type] => 1 [patent_app_number] => 8/581243 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 32 [patent_no_of_words] => 11906 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165826.pdf [firstpage_image] =>[orig_patent_app_number] => 581243 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/581243
Transistor with low resistance tip and method of fabrication in a CMOS process Dec 28, 1995 Issued
08/579703 METHOD OF MANUFACTURING A SELF-ALIGNED VERTICAL BIPOLAR TRANSISTOR ON AN SOI Dec 27, 1995 Abandoned
Array ( [id] => 3975906 [patent_doc_number] => 05937273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Fabricating compound semiconductor by varying ratio of stagnant layer thickness and mean free path of seed material' [patent_app_type] => 1 [patent_app_number] => 8/577399 [patent_app_country] => US [patent_app_date] => 1995-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 32 [patent_no_of_words] => 14410 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937273.pdf [firstpage_image] =>[orig_patent_app_number] => 577399 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/577399
Fabricating compound semiconductor by varying ratio of stagnant layer thickness and mean free path of seed material Dec 21, 1995 Issued
Array ( [id] => 3849624 [patent_doc_number] => 05767017 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Selective removal of vertical portions of a film' [patent_app_type] => 1 [patent_app_number] => 8/576186 [patent_app_country] => US [patent_app_date] => 1995-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2800 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767017.pdf [firstpage_image] =>[orig_patent_app_number] => 576186 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/576186
Selective removal of vertical portions of a film Dec 20, 1995 Issued
Array ( [id] => 3759552 [patent_doc_number] => 05851846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'Polishing method for SOI' [patent_app_type] => 1 [patent_app_number] => 8/576593 [patent_app_country] => US [patent_app_date] => 1995-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 42 [patent_no_of_words] => 8268 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/851/05851846.pdf [firstpage_image] =>[orig_patent_app_number] => 576593 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/576593
Polishing method for SOI Dec 20, 1995 Issued
Array ( [id] => 3728365 [patent_doc_number] => 05698063 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Intermediate workpiece employing a mask for etching an aperture aligned with the crystal planes in the workpiece substrate' [patent_app_type] => 1 [patent_app_number] => 8/575971 [patent_app_country] => US [patent_app_date] => 1995-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1946 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/698/05698063.pdf [firstpage_image] =>[orig_patent_app_number] => 575971 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/575971
Intermediate workpiece employing a mask for etching an aperture aligned with the crystal planes in the workpiece substrate Dec 20, 1995 Issued
Array ( [id] => 3620387 [patent_doc_number] => 05641692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'Method for producing a Bi-MOS device' [patent_app_type] => 1 [patent_app_number] => 8/574363 [patent_app_country] => US [patent_app_date] => 1995-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 4435 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/641/05641692.pdf [firstpage_image] =>[orig_patent_app_number] => 574363 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/574363
Method for producing a Bi-MOS device Dec 17, 1995 Issued
Array ( [id] => 3619734 [patent_doc_number] => 05614433 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'Method of fabricating low leakage SOI integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/573859 [patent_app_country] => US [patent_app_date] => 1995-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2089 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/614/05614433.pdf [firstpage_image] =>[orig_patent_app_number] => 573859 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/573859
Method of fabricating low leakage SOI integrated circuits Dec 17, 1995 Issued
Array ( [id] => 3700359 [patent_doc_number] => 05646074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Method of forming gate oxide for field effect transistor' [patent_app_type] => 1 [patent_app_number] => 8/573960 [patent_app_country] => US [patent_app_date] => 1995-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1764 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646074.pdf [firstpage_image] =>[orig_patent_app_number] => 573960 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/573960
Method of forming gate oxide for field effect transistor Dec 14, 1995 Issued
Array ( [id] => 3686866 [patent_doc_number] => 05643809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Method for making high speed poly-emitter bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/572449 [patent_app_country] => US [patent_app_date] => 1995-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3624 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/643/05643809.pdf [firstpage_image] =>[orig_patent_app_number] => 572449 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/572449
Method for making high speed poly-emitter bipolar transistor Dec 13, 1995 Issued
Array ( [id] => 3701232 [patent_doc_number] => 05674777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Method for forming silicon-boron binary compound layer as boron diffusion source in silicon electronic device' [patent_app_type] => 1 [patent_app_number] => 8/572495 [patent_app_country] => US [patent_app_date] => 1995-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2705 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/674/05674777.pdf [firstpage_image] =>[orig_patent_app_number] => 572495 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/572495
Method for forming silicon-boron binary compound layer as boron diffusion source in silicon electronic device Dec 13, 1995 Issued
Array ( [id] => 3832156 [patent_doc_number] => 05712198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Pre-thermal treatment cleaning process' [patent_app_type] => 1 [patent_app_number] => 8/568997 [patent_app_country] => US [patent_app_date] => 1995-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2459 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712198.pdf [firstpage_image] =>[orig_patent_app_number] => 568997 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/568997
Pre-thermal treatment cleaning process Dec 6, 1995 Issued
Array ( [id] => 3743069 [patent_doc_number] => 05801103 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Etching process which protects metal' [patent_app_type] => 1 [patent_app_number] => 8/566513 [patent_app_country] => US [patent_app_date] => 1995-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2525 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801103.pdf [firstpage_image] =>[orig_patent_app_number] => 566513 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/566513
Etching process which protects metal Dec 3, 1995 Issued
Array ( [id] => 3647382 [patent_doc_number] => 05683946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Method for manufacturing fluorinated gate oxide layer' [patent_app_type] => 1 [patent_app_number] => 8/565982 [patent_app_country] => US [patent_app_date] => 1995-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2359 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/683/05683946.pdf [firstpage_image] =>[orig_patent_app_number] => 565982 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/565982
Method for manufacturing fluorinated gate oxide layer Nov 30, 1995 Issued
Array ( [id] => 3768137 [patent_doc_number] => 05773340 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Method of manufacturing a BIMIS' [patent_app_type] => 1 [patent_app_number] => 8/563335 [patent_app_country] => US [patent_app_date] => 1995-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 9004 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/773/05773340.pdf [firstpage_image] =>[orig_patent_app_number] => 563335 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/563335
Method of manufacturing a BIMIS Nov 27, 1995 Issued
Array ( [id] => 3646976 [patent_doc_number] => 05629221 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Process for suppressing boron penetration in BF.sub.2 .sup.+ -implanted P.sup.+ -poly-Si gate using inductively-coupled nitrogen plasma' [patent_app_type] => 1 [patent_app_number] => 8/562465 [patent_app_country] => US [patent_app_date] => 1995-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2092 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/629/05629221.pdf [firstpage_image] =>[orig_patent_app_number] => 562465 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/562465
Process for suppressing boron penetration in BF.sub.2 .sup.+ -implanted P.sup.+ -poly-Si gate using inductively-coupled nitrogen plasma Nov 23, 1995 Issued
Array ( [id] => 3694206 [patent_doc_number] => 05650361 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Low temperature photolytic deposition of aluminum nitride thin films' [patent_app_type] => 1 [patent_app_number] => 8/560759 [patent_app_country] => US [patent_app_date] => 1995-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 5406 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/650/05650361.pdf [firstpage_image] =>[orig_patent_app_number] => 560759 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/560759
Low temperature photolytic deposition of aluminum nitride thin films Nov 20, 1995 Issued
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