
Long Pham
Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763 |
| Total Applications | 3774 |
| Issued Applications | 3306 |
| Pending Applications | 160 |
| Abandoned Applications | 335 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3855742
[patent_doc_number] => 05705423
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-06
[patent_title] => 'Epitaxial wafer'
[patent_app_type] => 1
[patent_app_number] => 8/557947
[patent_app_country] => US
[patent_app_date] => 1995-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5203
[patent_no_of_claims] => 2
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[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/705/05705423.pdf
[firstpage_image] =>[orig_patent_app_number] => 557947
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/557947 | Epitaxial wafer | Nov 13, 1995 | Issued |
Array
(
[id] => 3589592
[patent_doc_number] => 05567642
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-22
[patent_title] => 'Method of fabricating gate electrode of CMOS device'
[patent_app_type] => 1
[patent_app_number] => 8/554337
[patent_app_country] => US
[patent_app_date] => 1995-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 1484
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/567/05567642.pdf
[firstpage_image] =>[orig_patent_app_number] => 554337
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/554337 | Method of fabricating gate electrode of CMOS device | Nov 5, 1995 | Issued |
Array
(
[id] => 3645925
[patent_doc_number] => 05637525
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-10
[patent_title] => 'Method of forming a CMOS circuitry'
[patent_app_type] => 1
[patent_app_number] => 8/546149
[patent_app_country] => US
[patent_app_date] => 1995-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2772
[patent_no_of_claims] => 15
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/637/05637525.pdf
[firstpage_image] =>[orig_patent_app_number] => 546149
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/546149 | Method of forming a CMOS circuitry | Oct 19, 1995 | Issued |
Array
(
[id] => 3727197
[patent_doc_number] => 05670424
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-23
[patent_title] => 'Method for making local interconnect structure'
[patent_app_type] => 1
[patent_app_number] => 8/542815
[patent_app_country] => US
[patent_app_date] => 1995-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2237
[patent_no_of_claims] => 9
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/670/05670424.pdf
[firstpage_image] =>[orig_patent_app_number] => 542815
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/542815 | Method for making local interconnect structure | Oct 12, 1995 | Issued |
Array
(
[id] => 3626813
[patent_doc_number] => 05686319
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-11
[patent_title] => 'Method for producing a diode'
[patent_app_type] => 1
[patent_app_number] => 8/544417
[patent_app_country] => US
[patent_app_date] => 1995-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
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[patent_no_of_claims] => 9
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/686/05686319.pdf
[firstpage_image] =>[orig_patent_app_number] => 544417
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/544417 | Method for producing a diode | Oct 9, 1995 | Issued |
Array
(
[id] => 3692922
[patent_doc_number] => 05679588
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-21
[patent_title] => 'Method for fabricating P-wells and N-wells having optimized field and active regions'
[patent_app_type] => 1
[patent_app_number] => 8/539801
[patent_app_country] => US
[patent_app_date] => 1995-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 28
[patent_no_of_words] => 4017
[patent_no_of_claims] => 8
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/679/05679588.pdf
[firstpage_image] =>[orig_patent_app_number] => 539801
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/539801 | Method for fabricating P-wells and N-wells having optimized field and active regions | Oct 4, 1995 | Issued |
Array
(
[id] => 3705130
[patent_doc_number] => 05654213
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-05
[patent_title] => 'Method for fabricating a CMOS device'
[patent_app_type] => 1
[patent_app_number] => 8/538533
[patent_app_country] => US
[patent_app_date] => 1995-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 19
[patent_no_of_words] => 3270
[patent_no_of_claims] => 39
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[patent_words_short_claim] => 136
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/654/05654213.pdf
[firstpage_image] =>[orig_patent_app_number] => 538533
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/538533 | Method for fabricating a CMOS device | Oct 2, 1995 | Issued |
Array
(
[id] => 3855543
[patent_doc_number] => 05705409
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-06
[patent_title] => 'Method for forming trench transistor structure'
[patent_app_type] => 1
[patent_app_number] => 8/535397
[patent_app_country] => US
[patent_app_date] => 1995-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 50
[patent_no_of_words] => 9056
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 103
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/705/05705409.pdf
[firstpage_image] =>[orig_patent_app_number] => 535397
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/535397 | Method for forming trench transistor structure | Sep 27, 1995 | Issued |
Array
(
[id] => 3626898
[patent_doc_number] => 05686325
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-11
[patent_title] => 'Method for forming MESFET having T-shaped gate electrode'
[patent_app_type] => 1
[patent_app_number] => 8/531981
[patent_app_country] => US
[patent_app_date] => 1995-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 22
[patent_no_of_words] => 4968
[patent_no_of_claims] => 17
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[patent_words_short_claim] => 181
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/686/05686325.pdf
[firstpage_image] =>[orig_patent_app_number] => 531981
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/531981 | Method for forming MESFET having T-shaped gate electrode | Sep 20, 1995 | Issued |
Array
(
[id] => 3660678
[patent_doc_number] => 05656548
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-12
[patent_title] => 'Method for forming three dimensional processor using transferred thin film circuits'
[patent_app_type] => 1
[patent_app_number] => 8/531177
[patent_app_country] => US
[patent_app_date] => 1995-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 27
[patent_no_of_words] => 8475
[patent_no_of_claims] => 63
[patent_no_of_ind_claims] => 7
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/656/05656548.pdf
[firstpage_image] =>[orig_patent_app_number] => 531177
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/531177 | Method for forming three dimensional processor using transferred thin film circuits | Sep 18, 1995 | Issued |
| 08/528123 | PROCESS FOR PRODUCING SEMICONDUCTOR DEVICES | Sep 13, 1995 | Abandoned |
Array
(
[id] => 3686994
[patent_doc_number] => 05696034
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'Method for producing semiconductor substrate'
[patent_app_type] => 1
[patent_app_number] => 8/520189
[patent_app_country] => US
[patent_app_date] => 1995-08-28
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/696/05696034.pdf
[firstpage_image] =>[orig_patent_app_number] => 520189
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/520189 | Method for producing semiconductor substrate | Aug 27, 1995 | Issued |
Array
(
[id] => 3847627
[patent_doc_number] => 05719082
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-17
[patent_title] => 'Angled implant to improve high current operation of bipolar transistors'
[patent_app_type] => 1
[patent_app_number] => 8/519817
[patent_app_country] => US
[patent_app_date] => 1995-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/719/05719082.pdf
[firstpage_image] =>[orig_patent_app_number] => 519817
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/519817 | Angled implant to improve high current operation of bipolar transistors | Aug 24, 1995 | Issued |
Array
(
[id] => 3855886
[patent_doc_number] => 05705433
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-06
[patent_title] => 'Etching silicon-containing materials by use of silicon-containing compounds'
[patent_app_type] => 1
[patent_app_number] => 8/518937
[patent_app_country] => US
[patent_app_date] => 1995-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 2055
[patent_no_of_claims] => 10
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/705/05705433.pdf
[firstpage_image] =>[orig_patent_app_number] => 518937
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/518937 | Etching silicon-containing materials by use of silicon-containing compounds | Aug 23, 1995 | Issued |
Array
(
[id] => 3694713
[patent_doc_number] => 05661073
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-26
[patent_title] => 'Method for forming field oxide having uniform thickness'
[patent_app_type] => 1
[patent_app_number] => 8/514159
[patent_app_country] => US
[patent_app_date] => 1995-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 1482
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[patent_words_short_claim] => 129
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/661/05661073.pdf
[firstpage_image] =>[orig_patent_app_number] => 514159
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/514159 | Method for forming field oxide having uniform thickness | Aug 10, 1995 | Issued |
Array
(
[id] => 3832160
[patent_doc_number] => 05814534
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-29
[patent_title] => 'Method of doping with beryllium and method of fabricating semiconductor optical element doped with beryllium'
[patent_app_type] => 1
[patent_app_number] => 8/510695
[patent_app_country] => US
[patent_app_date] => 1995-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/814/05814534.pdf
[firstpage_image] =>[orig_patent_app_number] => 510695
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/510695 | Method of doping with beryllium and method of fabricating semiconductor optical element doped with beryllium | Aug 2, 1995 | Issued |
Array
(
[id] => 3549633
[patent_doc_number] => 05571745
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-05
[patent_title] => 'Fabrication method of semiconductor device containing n- and p-channel MOSFETs'
[patent_app_type] => 1
[patent_app_number] => 8/510103
[patent_app_country] => US
[patent_app_date] => 1995-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 7232
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/571/05571745.pdf
[firstpage_image] =>[orig_patent_app_number] => 510103
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/510103 | Fabrication method of semiconductor device containing n- and p-channel MOSFETs | Jul 31, 1995 | Issued |
Array
(
[id] => 3612664
[patent_doc_number] => 05534449
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-09
[patent_title] => 'Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry'
[patent_app_type] => 1
[patent_app_number] => 8/503419
[patent_app_country] => US
[patent_app_date] => 1995-07-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/534/05534449.pdf
[firstpage_image] =>[orig_patent_app_number] => 503419
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/503419 | Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry | Jul 16, 1995 | Issued |
Array
(
[id] => 3726776
[patent_doc_number] => 05670393
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-23
[patent_title] => 'Method of making combined metal oxide semiconductor and junction field effect transistor device'
[patent_app_type] => 1
[patent_app_number] => 8/501289
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[pdf_file] => patents/05/670/05670393.pdf
[firstpage_image] =>[orig_patent_app_number] => 501289
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/501289 | Method of making combined metal oxide semiconductor and junction field effect transistor device | Jul 11, 1995 | Issued |
Array
(
[id] => 3552271
[patent_doc_number] => 05573960
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-12
[patent_title] => 'Method of manufacturing semiconductor layers by bonding without defects created by bonding'
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[pdf_file] => patents/05/573/05573960.pdf
[firstpage_image] =>[orig_patent_app_number] => 500247
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/500247 | Method of manufacturing semiconductor layers by bonding without defects created by bonding | Jul 9, 1995 | Issued |