Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3645746 [patent_doc_number] => 05637513 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-10 [patent_title] => 'Fabrication method of semiconductor device with SOI structure' [patent_app_type] => 1 [patent_app_number] => 8/499493 [patent_app_country] => US [patent_app_date] => 1995-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 5636 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/637/05637513.pdf [firstpage_image] =>[orig_patent_app_number] => 499493 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/499493
Fabrication method of semiconductor device with SOI structure Jul 6, 1995 Issued
Array ( [id] => 3657736 [patent_doc_number] => 05627097 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-06 [patent_title] => 'Method for making CMOS device having reduced parasitic capacitance' [patent_app_type] => 1 [patent_app_number] => 8/498709 [patent_app_country] => US [patent_app_date] => 1995-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3816 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/627/05627097.pdf [firstpage_image] =>[orig_patent_app_number] => 498709 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/498709
Method for making CMOS device having reduced parasitic capacitance Jul 2, 1995 Issued
Array ( [id] => 3660083 [patent_doc_number] => 05648279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Method of manufacturing bipolar transistor having emitter region and external base region formed in self alignment manner' [patent_app_type] => 1 [patent_app_number] => 8/491719 [patent_app_country] => US [patent_app_date] => 1995-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 39 [patent_no_of_words] => 6002 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 407 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/648/05648279.pdf [firstpage_image] =>[orig_patent_app_number] => 491719 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/491719
Method of manufacturing bipolar transistor having emitter region and external base region formed in self alignment manner Jun 18, 1995 Issued
Array ( [id] => 3574312 [patent_doc_number] => 05523246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Method of fabricating a high-voltage metal-gate CMOS device' [patent_app_type] => 1 [patent_app_number] => 8/490221 [patent_app_country] => US [patent_app_date] => 1995-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1912 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/523/05523246.pdf [firstpage_image] =>[orig_patent_app_number] => 490221 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/490221
Method of fabricating a high-voltage metal-gate CMOS device Jun 13, 1995 Issued
Array ( [id] => 3524361 [patent_doc_number] => 05504018 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-02 [patent_title] => 'Process of fabricating bipolar transistor having epitaxially grown base layer without deterioration of transistor characteristics' [patent_app_type] => 1 [patent_app_number] => 8/490475 [patent_app_country] => US [patent_app_date] => 1995-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 7822 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/504/05504018.pdf [firstpage_image] =>[orig_patent_app_number] => 490475 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/490475
Process of fabricating bipolar transistor having epitaxially grown base layer without deterioration of transistor characteristics Jun 13, 1995 Issued
Array ( [id] => 3647921 [patent_doc_number] => 05639694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Method for making single layer leadframe having groundplane capability' [patent_app_type] => 1 [patent_app_number] => 8/480299 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7424 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/639/05639694.pdf [firstpage_image] =>[orig_patent_app_number] => 480299 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/480299
Method for making single layer leadframe having groundplane capability Jun 6, 1995 Issued
Array ( [id] => 3725177 [patent_doc_number] => 05700701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Method for reducing junction capacitance and increasing current gain in collector-up bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 8/472081 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 2205 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/700/05700701.pdf [firstpage_image] =>[orig_patent_app_number] => 472081 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/472081
Method for reducing junction capacitance and increasing current gain in collector-up bipolar transistors Jun 6, 1995 Issued
Array ( [id] => 3529495 [patent_doc_number] => 05583062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Self-aligned twin well process having a SiO.sub.2 -polysilicon-SiO.sub.2 barrier mask' [patent_app_type] => 1 [patent_app_number] => 8/488075 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2360 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/583/05583062.pdf [firstpage_image] =>[orig_patent_app_number] => 488075 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/488075
Self-aligned twin well process having a SiO.sub.2 -polysilicon-SiO.sub.2 barrier mask Jun 6, 1995 Issued
Array ( [id] => 3726876 [patent_doc_number] => 05702973 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Method for forming epitaxial semiconductor wafer for CMOS integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/477997 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4171 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/702/05702973.pdf [firstpage_image] =>[orig_patent_app_number] => 477997 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/477997
Method for forming epitaxial semiconductor wafer for CMOS integrated circuits Jun 6, 1995 Issued
Array ( [id] => 3525801 [patent_doc_number] => 05541124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-30 [patent_title] => 'Method for making bipolar transistor having double polysilicon structure' [patent_app_type] => 1 [patent_app_number] => 8/477471 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 93 [patent_no_of_words] => 18684 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/541/05541124.pdf [firstpage_image] =>[orig_patent_app_number] => 477471 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/477471
Method for making bipolar transistor having double polysilicon structure Jun 6, 1995 Issued
Array ( [id] => 1542622 [patent_doc_number] => 06372596 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Method of making horizontal bipolar transistor with insulated base structure' [patent_app_type] => B1 [patent_app_number] => 08/474239 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1656 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372596.pdf [firstpage_image] =>[orig_patent_app_number] => 08474239 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/474239
Method of making horizontal bipolar transistor with insulated base structure Jun 6, 1995 Issued
Array ( [id] => 3513882 [patent_doc_number] => 05512496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-30 [patent_title] => 'Method of making collector-up bipolar transistor having improved emitter injection efficiency' [patent_app_type] => 1 [patent_app_number] => 8/483001 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 4602 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/512/05512496.pdf [firstpage_image] =>[orig_patent_app_number] => 483001 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/483001
Method of making collector-up bipolar transistor having improved emitter injection efficiency Jun 6, 1995 Issued
Array ( [id] => 3954789 [patent_doc_number] => 05935867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Shallow drain extension formation by angled implantation' [patent_app_type] => 1 [patent_app_number] => 8/481895 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3088 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/935/05935867.pdf [firstpage_image] =>[orig_patent_app_number] => 481895 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/481895
Shallow drain extension formation by angled implantation Jun 6, 1995 Issued
08/479739 REDUCING EXTRINSIC BASE-COLLECTOR CAPACITANCE Jun 6, 1995 Abandoned
Array ( [id] => 3686822 [patent_doc_number] => 05643806 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Manufacturing method for making bipolar device' [patent_app_type] => 1 [patent_app_number] => 8/472869 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 93 [patent_no_of_words] => 18685 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/643/05643806.pdf [firstpage_image] =>[orig_patent_app_number] => 472869 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/472869
Manufacturing method for making bipolar device Jun 6, 1995 Issued
Array ( [id] => 3950362 [patent_doc_number] => 05899714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Fabrication of semiconductor structure having two levels of buried regions' [patent_app_type] => 1 [patent_app_number] => 8/471061 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 119 [patent_no_of_words] => 27827 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/899/05899714.pdf [firstpage_image] =>[orig_patent_app_number] => 471061 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/471061
Fabrication of semiconductor structure having two levels of buried regions Jun 5, 1995 Issued
Array ( [id] => 3517382 [patent_doc_number] => 05506157 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-09 [patent_title] => 'Method for fabricating pillar bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/469677 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 2884 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/506/05506157.pdf [firstpage_image] =>[orig_patent_app_number] => 469677 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/469677
Method for fabricating pillar bipolar transistor Jun 5, 1995 Issued
Array ( [id] => 3730751 [patent_doc_number] => 05665614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Method for making fully self-aligned submicron heterojunction bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/470811 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4589 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/665/05665614.pdf [firstpage_image] =>[orig_patent_app_number] => 470811 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/470811
Method for making fully self-aligned submicron heterojunction bipolar transistor Jun 5, 1995 Issued
Array ( [id] => 3641562 [patent_doc_number] => 05628870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Method for marking a substrate using ionized gas' [patent_app_type] => 1 [patent_app_number] => 8/458961 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1909 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/628/05628870.pdf [firstpage_image] =>[orig_patent_app_number] => 458961 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/458961
Method for marking a substrate using ionized gas Jun 4, 1995 Issued
Array ( [id] => 3589764 [patent_doc_number] => 05567655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Method for forming interior bond pads having zig-zag linear arrangement' [patent_app_type] => 1 [patent_app_number] => 8/469086 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4746 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/567/05567655.pdf [firstpage_image] =>[orig_patent_app_number] => 469086 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/469086
Method for forming interior bond pads having zig-zag linear arrangement Jun 4, 1995 Issued
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