Long Pham

Array ( [id] => 3537939 [patent_doc_number] => 05494836 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'Process of producing heterojunction bipolar transistor with silicon-germanium base' [patent_app_type] => 1 [patent_app_number] => 8/460259 [patent_app_country] => US [patent_app_date] => 1995-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 4321 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/494/05494836.pdf [firstpage_image] =>[orig_patent_app_number] => 460259 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3681694 [patent_doc_number] => 05633180 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Method of forming P-type islands over P-type buried layer' [patent_app_type] => 1 [patent_app_number] => 8/456727 [patent_app_country] => US [patent_app_date] => 1995-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1687 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/633/05633180.pdf [firstpage_image] =>[orig_patent_app_number] => 456727 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3588597 [patent_doc_number] => 05585287 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Method of forming integrated current-limiter device for power MOS transistors' [patent_app_type] => 1 [patent_app_number] => 8/458055 [patent_app_country] => US [patent_app_date] => 1995-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2587 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/585/05585287.pdf [firstpage_image] =>[orig_patent_app_number] => 458055 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3655954 [patent_doc_number] => 05622876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Method for making monolithic integrated bridge transistor circuit' [patent_app_type] => 1 [patent_app_number] => 8/458083 [patent_app_country] => US [patent_app_date] => 1995-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2402 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/622/05622876.pdf [firstpage_image] =>[orig_patent_app_number] => 458083 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3726661 [patent_doc_number] => 05702959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Method for making an isolated vertical transistor' [patent_app_type] => 1 [patent_app_number] => 8/455945 [patent_app_country] => US [patent_app_date] => 1995-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 4794 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/702/05702959.pdf [firstpage_image] =>[orig_patent_app_number] => 455945 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3836713 [patent_doc_number] => 05846868 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Method for forming a walled-emitter transistor' [patent_app_type] => 1 [patent_app_number] => 8/456911 [patent_app_country] => US [patent_app_date] => 1995-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2017 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/846/05846868.pdf [firstpage_image] =>[orig_patent_app_number] => 456911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3543638 [patent_doc_number] => 05554543 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-10 [patent_title] => 'Process for fabricating bipolar junction transistor having reduced parasitic capacitance' [patent_app_type] => 1 [patent_app_number] => 8/449625 [patent_app_country] => US [patent_app_date] => 1995-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2104 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/554/05554543.pdf [firstpage_image] =>[orig_patent_app_number] => 449625 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3509516 [patent_doc_number] => 05587327 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'Process for preparing a heterojunction bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/447947 [patent_app_country] => US [patent_app_date] => 1995-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 2643 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/587/05587327.pdf [firstpage_image] =>[orig_patent_app_number] => 447947 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3660940 [patent_doc_number] => 05624854 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Method of formation of bipolar transistor having reduced parasitic capacitance' [patent_app_type] => 1 [patent_app_number] => 8/446397 [patent_app_country] => US [patent_app_date] => 1995-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2312 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/624/05624854.pdf [firstpage_image] =>[orig_patent_app_number] => 446397 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3694671 [patent_doc_number] => 05618748 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-08 [patent_title] => 'Manufacturing method of CMOS transistor with no reduction of punch-through voltage' [patent_app_type] => 1 [patent_app_number] => 8/443266 [patent_app_country] => US [patent_app_date] => 1995-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 51 [patent_no_of_words] => 11759 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/618/05618748.pdf [firstpage_image] =>[orig_patent_app_number] => 443266 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3805985 [patent_doc_number] => 05854097 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/440917 [patent_app_country] => US [patent_app_date] => 1995-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 41 [patent_no_of_words] => 11893 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854097.pdf [firstpage_image] =>[orig_patent_app_number] => 440917 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3622807 [patent_doc_number] => 05612245 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'Method of manufacturing CMOS device' [patent_app_type] => 1 [patent_app_number] => 8/434406 [patent_app_country] => US [patent_app_date] => 1995-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 4839 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/612/05612245.pdf [firstpage_image] =>[orig_patent_app_number] => 434406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3701045 [patent_doc_number] => 05674763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/428827 [patent_app_country] => US [patent_app_date] => 1995-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 87 [patent_no_of_words] => 14498 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/674/05674763.pdf [firstpage_image] =>[orig_patent_app_number] => 428827 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3532767 [patent_doc_number] => 05556796 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-17 [patent_title] => 'Self-alignment technique for forming junction isolation and wells' [patent_app_type] => 1 [patent_app_number] => 8/428929 [patent_app_country] => US [patent_app_date] => 1995-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2482 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/556/05556796.pdf [firstpage_image] =>[orig_patent_app_number] => 428929 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3607879 [patent_doc_number] => 05589405 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Method for fabricating VDMOS transistor with improved breakdown characteristics' [patent_app_type] => 1 [patent_app_number] => 8/403629 [patent_app_country] => US [patent_app_date] => 1995-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4082 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/589/05589405.pdf [firstpage_image] =>[orig_patent_app_number] => 403629 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3660928 [patent_doc_number] => 05624853 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Method for forming heterojunction bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 8/417781 [patent_app_country] => US [patent_app_date] => 1995-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 48 [patent_no_of_words] => 8229 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/624/05624853.pdf [firstpage_image] =>[orig_patent_app_number] => 417781 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3620373 [patent_doc_number] => 05641691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'Method for fabricating complementary vertical bipolar junction transistors in silicon-on-sapphire' [patent_app_type] => 1 [patent_app_number] => 8/415389 [patent_app_country] => US [patent_app_date] => 1995-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2101 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/641/05641691.pdf [firstpage_image] =>[orig_patent_app_number] => 415389 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3729919 [patent_doc_number] => 05635414 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'Low cost method of fabricating shallow junction, Schottky semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/409762 [patent_app_country] => US [patent_app_date] => 1995-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1697 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/635/05635414.pdf [firstpage_image] =>[orig_patent_app_number] => 409762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3492918 [patent_doc_number] => 05561086 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-01 [patent_title] => 'Techniques for mounting semiconductor dies in die-receiving areas having support structure having notches' [patent_app_type] => 1 [patent_app_number] => 8/412597 [patent_app_country] => US [patent_app_date] => 1995-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6543 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/561/05561086.pdf [firstpage_image] =>[orig_patent_app_number] => 412597 [rel_patent_id] =>[rel_patent_doc_number] =>)