Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3492918 [patent_doc_number] => 05561086 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-01 [patent_title] => 'Techniques for mounting semiconductor dies in die-receiving areas having support structure having notches' [patent_app_type] => 1 [patent_app_number] => 8/412597 [patent_app_country] => US [patent_app_date] => 1995-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6543 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/561/05561086.pdf [firstpage_image] =>[orig_patent_app_number] => 412597 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/412597
Techniques for mounting semiconductor dies in die-receiving areas having support structure having notches Mar 26, 1995 Issued
Array ( [id] => 3696869 [patent_doc_number] => 05677208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Method for making FET having reduced oxidation inductive stacking fault' [patent_app_type] => 1 [patent_app_number] => 8/410373 [patent_app_country] => US [patent_app_date] => 1995-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 57 [patent_no_of_words] => 7447 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677208.pdf [firstpage_image] =>[orig_patent_app_number] => 410373 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/410373
Method for making FET having reduced oxidation inductive stacking fault Mar 23, 1995 Issued
Array ( [id] => 3625032 [patent_doc_number] => 05620922 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-15 [patent_title] => 'Method for fabricating CMOS device having low and high resistance portions and wire formed from a single gate polysilicon' [patent_app_type] => 1 [patent_app_number] => 8/414003 [patent_app_country] => US [patent_app_date] => 1995-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 44 [patent_no_of_words] => 10852 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/620/05620922.pdf [firstpage_image] =>[orig_patent_app_number] => 414003 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/414003
Method for fabricating CMOS device having low and high resistance portions and wire formed from a single gate polysilicon Mar 16, 1995 Issued
Array ( [id] => 3611510 [patent_doc_number] => 05565375 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'Method of fabricating a self-cascoding CMOS device' [patent_app_type] => 1 [patent_app_number] => 8/407487 [patent_app_country] => US [patent_app_date] => 1995-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 10250 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/565/05565375.pdf [firstpage_image] =>[orig_patent_app_number] => 407487 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/407487
Method of fabricating a self-cascoding CMOS device Mar 15, 1995 Issued
Array ( [id] => 3694516 [patent_doc_number] => 05618738 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-08 [patent_title] => 'Manufacturing method for magnetoresistance elements' [patent_app_type] => 1 [patent_app_number] => 8/404147 [patent_app_country] => US [patent_app_date] => 1995-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5313 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/618/05618738.pdf [firstpage_image] =>[orig_patent_app_number] => 404147 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/404147
Manufacturing method for magnetoresistance elements Mar 13, 1995 Issued
Array ( [id] => 3620545 [patent_doc_number] => 05641704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'Method of isolating active areas of a semiconductor substrate by shallow trenches and narrow trenches' [patent_app_type] => 1 [patent_app_number] => 8/403143 [patent_app_country] => US [patent_app_date] => 1995-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 3729 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/641/05641704.pdf [firstpage_image] =>[orig_patent_app_number] => 403143 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/403143
Method of isolating active areas of a semiconductor substrate by shallow trenches and narrow trenches Mar 12, 1995 Issued
Array ( [id] => 3824443 [patent_doc_number] => 05731228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Method for making micro electron beam source' [patent_app_type] => 1 [patent_app_number] => 8/401511 [patent_app_country] => US [patent_app_date] => 1995-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 92 [patent_no_of_words] => 15806 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/731/05731228.pdf [firstpage_image] =>[orig_patent_app_number] => 401511 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/401511
Method for making micro electron beam source Mar 9, 1995 Issued
Array ( [id] => 3664325 [patent_doc_number] => 05597738 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Method for forming isolated CMOS structures on SOI structures' [patent_app_type] => 1 [patent_app_number] => 8/400139 [patent_app_country] => US [patent_app_date] => 1995-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 2928 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/597/05597738.pdf [firstpage_image] =>[orig_patent_app_number] => 400139 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/400139
Method for forming isolated CMOS structures on SOI structures Mar 5, 1995 Issued
Array ( [id] => 3566591 [patent_doc_number] => 05484738 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Method of forming silicon on oxide semiconductor device structure for BiCMOS integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/396985 [patent_app_country] => US [patent_app_date] => 1995-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 1700 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/484/05484738.pdf [firstpage_image] =>[orig_patent_app_number] => 396985 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/396985
Method of forming silicon on oxide semiconductor device structure for BiCMOS integrated circuits Feb 28, 1995 Issued
Array ( [id] => 3607938 [patent_doc_number] => 05589409 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Fabrication of bipolar transistors with improved output current-voltage characteristics' [patent_app_type] => 1 [patent_app_number] => 8/393647 [patent_app_country] => US [patent_app_date] => 1995-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 51 [patent_no_of_words] => 12682 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/589/05589409.pdf [firstpage_image] =>[orig_patent_app_number] => 393647 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/393647
Fabrication of bipolar transistors with improved output current-voltage characteristics Feb 23, 1995 Issued
Array ( [id] => 3894479 [patent_doc_number] => 05750422 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Method for making integrated circuit packaging with reinforced leads' [patent_app_type] => 1 [patent_app_number] => 8/394043 [patent_app_country] => US [patent_app_date] => 1995-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 4689 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/750/05750422.pdf [firstpage_image] =>[orig_patent_app_number] => 394043 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/394043
Method for making integrated circuit packaging with reinforced leads Feb 23, 1995 Issued
Array ( [id] => 3621224 [patent_doc_number] => 05593905 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Method of forming stacked barrier-diffusion source and etch stop for double polysilicon BJT with patterned base link' [patent_app_type] => 1 [patent_app_number] => 8/392597 [patent_app_country] => US [patent_app_date] => 1995-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 2582 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/593/05593905.pdf [firstpage_image] =>[orig_patent_app_number] => 392597 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/392597
Method of forming stacked barrier-diffusion source and etch stop for double polysilicon BJT with patterned base link Feb 22, 1995 Issued
Array ( [id] => 3597863 [patent_doc_number] => 05559045 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Method of fabricating vertical-type double diffused mosfet having a self-aligned field oxide film' [patent_app_type] => 1 [patent_app_number] => 8/409614 [patent_app_country] => US [patent_app_date] => 1995-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3483 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559045.pdf [firstpage_image] =>[orig_patent_app_number] => 409614 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/409614
Method of fabricating vertical-type double diffused mosfet having a self-aligned field oxide film Feb 12, 1995 Issued
Array ( [id] => 3633697 [patent_doc_number] => 05631196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-20 [patent_title] => 'Method for making inversion mode diamond electron source' [patent_app_type] => 1 [patent_app_number] => 8/385027 [patent_app_country] => US [patent_app_date] => 1995-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2264 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/631/05631196.pdf [firstpage_image] =>[orig_patent_app_number] => 385027 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/385027
Method for making inversion mode diamond electron source Feb 6, 1995 Issued
Array ( [id] => 3687666 [patent_doc_number] => 05691241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Method for making plurality of leadframes having grooves containing island and inner leads' [patent_app_type] => 1 [patent_app_number] => 8/383573 [patent_app_country] => US [patent_app_date] => 1995-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4359 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/691/05691241.pdf [firstpage_image] =>[orig_patent_app_number] => 383573 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/383573
Method for making plurality of leadframes having grooves containing island and inner leads Feb 2, 1995 Issued
Array ( [id] => 3428242 [patent_doc_number] => 05455188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-03 [patent_title] => 'Process for fabricating a lateral bipolar junction transistor' [patent_app_type] => 1 [patent_app_number] => 8/381133 [patent_app_country] => US [patent_app_date] => 1995-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 2423 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/455/05455188.pdf [firstpage_image] =>[orig_patent_app_number] => 381133 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/381133
Process for fabricating a lateral bipolar junction transistor Jan 30, 1995 Issued
Array ( [id] => 3552408 [patent_doc_number] => 05573969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Method for fabrication of CMOS devices having minimized drain contact area' [patent_app_type] => 1 [patent_app_number] => 8/375551 [patent_app_country] => US [patent_app_date] => 1995-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1750 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/573/05573969.pdf [firstpage_image] =>[orig_patent_app_number] => 375551 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/375551
Method for fabrication of CMOS devices having minimized drain contact area Jan 18, 1995 Issued
Array ( [id] => 3687058 [patent_doc_number] => 05643822 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Method for forming trench-isolated FET devices' [patent_app_type] => 1 [patent_app_number] => 8/370703 [patent_app_country] => US [patent_app_date] => 1995-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4822 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/643/05643822.pdf [firstpage_image] =>[orig_patent_app_number] => 370703 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/370703
Method for forming trench-isolated FET devices Jan 9, 1995 Issued
Array ( [id] => 3687101 [patent_doc_number] => 05643825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Integrated circuit isolation process' [patent_app_type] => 1 [patent_app_number] => 8/366053 [patent_app_country] => US [patent_app_date] => 1994-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4901 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/643/05643825.pdf [firstpage_image] =>[orig_patent_app_number] => 366053 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/366053
Integrated circuit isolation process Dec 28, 1994 Issued
08/361993 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Dec 20, 1994 Abandoned
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