Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3589022 [patent_doc_number] => 05496745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-05 [patent_title] => 'Method for making bipolar transistor having an enhanced trench isolation' [patent_app_type] => 1 [patent_app_number] => 8/358825 [patent_app_country] => US [patent_app_date] => 1994-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 24 [patent_no_of_words] => 3890 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/496/05496745.pdf [firstpage_image] =>[orig_patent_app_number] => 358825 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/358825
Method for making bipolar transistor having an enhanced trench isolation Dec 18, 1994 Issued
Array ( [id] => 3729931 [patent_doc_number] => 05693548 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Method for making T-gate of field effect transistor' [patent_app_type] => 1 [patent_app_number] => 8/359197 [patent_app_country] => US [patent_app_date] => 1994-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 1956 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/693/05693548.pdf [firstpage_image] =>[orig_patent_app_number] => 359197 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/359197
Method for making T-gate of field effect transistor Dec 18, 1994 Issued
Array ( [id] => 3419358 [patent_doc_number] => 05478771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'Method of forming local interconnect structure without P-N junction between active elements' [patent_app_type] => 1 [patent_app_number] => 8/359006 [patent_app_country] => US [patent_app_date] => 1994-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2237 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/478/05478771.pdf [firstpage_image] =>[orig_patent_app_number] => 359006 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/359006
Method of forming local interconnect structure without P-N junction between active elements Dec 18, 1994 Issued
Array ( [id] => 3423619 [patent_doc_number] => 05459084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Method for fabricating hetero-junction bipolar transistor having reduced base parasitic resistance' [patent_app_type] => 1 [patent_app_number] => 8/358533 [patent_app_country] => US [patent_app_date] => 1994-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2879 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459084.pdf [firstpage_image] =>[orig_patent_app_number] => 358533 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/358533
Method for fabricating hetero-junction bipolar transistor having reduced base parasitic resistance Dec 18, 1994 Issued
Array ( [id] => 3791457 [patent_doc_number] => 05726069 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Use of oblique implantation in forming emitter of bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/348629 [patent_app_country] => US [patent_app_date] => 1994-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 30 [patent_no_of_words] => 7908 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726069.pdf [firstpage_image] =>[orig_patent_app_number] => 348629 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/348629
Use of oblique implantation in forming emitter of bipolar transistor Dec 1, 1994 Issued
Array ( [id] => 3529509 [patent_doc_number] => 05583063 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Method of forming T-shaped, cross-sectional pattern using two layered masks' [patent_app_type] => 1 [patent_app_number] => 8/346401 [patent_app_country] => US [patent_app_date] => 1994-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 4130 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/583/05583063.pdf [firstpage_image] =>[orig_patent_app_number] => 346401 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/346401
Method of forming T-shaped, cross-sectional pattern using two layered masks Nov 28, 1994 Issued
Array ( [id] => 3587144 [patent_doc_number] => 05550065 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'Method of fabricating self-aligned FET structure having a high temperature stable T-shaped Schottky gate contact' [patent_app_type] => 1 [patent_app_number] => 8/344911 [patent_app_country] => US [patent_app_date] => 1994-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 1951 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/550/05550065.pdf [firstpage_image] =>[orig_patent_app_number] => 344911 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/344911
Method of fabricating self-aligned FET structure having a high temperature stable T-shaped Schottky gate contact Nov 24, 1994 Issued
Array ( [id] => 3660172 [patent_doc_number] => 05656514 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Method for making heterojunction bipolar transistor with self-aligned retrograde emitter profile' [patent_app_type] => 1 [patent_app_number] => 8/346209 [patent_app_country] => US [patent_app_date] => 1994-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4825 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/656/05656514.pdf [firstpage_image] =>[orig_patent_app_number] => 346209 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/346209
Method for making heterojunction bipolar transistor with self-aligned retrograde emitter profile Nov 21, 1994 Issued
Array ( [id] => 3587625 [patent_doc_number] => 05516709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'Method of manufacturing bipolar transistor with reduced numbers of steps without increasing collector resistance' [patent_app_type] => 1 [patent_app_number] => 8/346163 [patent_app_country] => US [patent_app_date] => 1994-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 7032 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/516/05516709.pdf [firstpage_image] =>[orig_patent_app_number] => 346163 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/346163
Method of manufacturing bipolar transistor with reduced numbers of steps without increasing collector resistance Nov 20, 1994 Issued
Array ( [id] => 3660395 [patent_doc_number] => 05648300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Method of manufacturing cantilever drive mechanism and probe drive mechanism' [patent_app_type] => 1 [patent_app_number] => 8/344585 [patent_app_country] => US [patent_app_date] => 1994-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 35 [patent_no_of_words] => 14380 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/648/05648300.pdf [firstpage_image] =>[orig_patent_app_number] => 344585 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/344585
Method of manufacturing cantilever drive mechanism and probe drive mechanism Nov 17, 1994 Issued
Array ( [id] => 3587607 [patent_doc_number] => 05516708 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'Method of making single polysilicon self-aligned bipolar transistor having reduced emitter-base junction' [patent_app_type] => 1 [patent_app_number] => 8/342041 [patent_app_country] => US [patent_app_date] => 1994-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2846 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/516/05516708.pdf [firstpage_image] =>[orig_patent_app_number] => 342041 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/342041
Method of making single polysilicon self-aligned bipolar transistor having reduced emitter-base junction Nov 16, 1994 Issued
Array ( [id] => 3101954 [patent_doc_number] => 05447872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Manufacturing method of CMOS transistor including heat treatments of gate electrodes and LDD regions at reducing temperatures' [patent_app_type] => 1 [patent_app_number] => 8/340375 [patent_app_country] => US [patent_app_date] => 1994-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 51 [patent_no_of_words] => 11755 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/447/05447872.pdf [firstpage_image] =>[orig_patent_app_number] => 340375 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/340375
Manufacturing method of CMOS transistor including heat treatments of gate electrodes and LDD regions at reducing temperatures Nov 13, 1994 Issued
Array ( [id] => 3472305 [patent_doc_number] => 05476813 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-19 [patent_title] => 'Method of manufacturing a bonded semiconductor substrate and a dielectric isolated bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/340361 [patent_app_country] => US [patent_app_date] => 1994-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 22 [patent_no_of_words] => 3425 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/476/05476813.pdf [firstpage_image] =>[orig_patent_app_number] => 340361 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/340361
Method of manufacturing a bonded semiconductor substrate and a dielectric isolated bipolar transistor Nov 13, 1994 Issued
Array ( [id] => 3589003 [patent_doc_number] => 05496744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-05 [patent_title] => 'Method of fabricating complementary poly emitter transistors' [patent_app_type] => 1 [patent_app_number] => 8/338691 [patent_app_country] => US [patent_app_date] => 1994-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3475 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/496/05496744.pdf [firstpage_image] =>[orig_patent_app_number] => 338691 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/338691
Method of fabricating complementary poly emitter transistors Nov 13, 1994 Issued
Array ( [id] => 3525746 [patent_doc_number] => 05541120 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-30 [patent_title] => 'Method of making complementary bipolar polysilicon emitter devices' [patent_app_type] => 1 [patent_app_number] => 8/337154 [patent_app_country] => US [patent_app_date] => 1994-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 5155 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/541/05541120.pdf [firstpage_image] =>[orig_patent_app_number] => 337154 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/337154
Method of making complementary bipolar polysilicon emitter devices Nov 8, 1994 Issued
Array ( [id] => 3481988 [patent_doc_number] => 05445979 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Method of making field effect compound semiconductor device with eaves electrode' [patent_app_type] => 1 [patent_app_number] => 8/330583 [patent_app_country] => US [patent_app_date] => 1994-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3973 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/445/05445979.pdf [firstpage_image] =>[orig_patent_app_number] => 330583 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/330583
Method of making field effect compound semiconductor device with eaves electrode Oct 27, 1994 Issued
Array ( [id] => 3517442 [patent_doc_number] => 05506161 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-09 [patent_title] => 'Method of manufacturing graded channels underneath the gate electrode extensions' [patent_app_type] => 1 [patent_app_number] => 8/328317 [patent_app_country] => US [patent_app_date] => 1994-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5949 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/506/05506161.pdf [firstpage_image] =>[orig_patent_app_number] => 328317 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/328317
Method of manufacturing graded channels underneath the gate electrode extensions Oct 23, 1994 Issued
Array ( [id] => 3655970 [patent_doc_number] => 05622877 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Method for making high-voltage high-speed gallium arsenide power Schottky diode' [patent_app_type] => 1 [patent_app_number] => 8/326893 [patent_app_country] => US [patent_app_date] => 1994-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 3532 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/622/05622877.pdf [firstpage_image] =>[orig_patent_app_number] => 326893 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/326893
Method for making high-voltage high-speed gallium arsenide power Schottky diode Oct 20, 1994 Issued
Array ( [id] => 3727035 [patent_doc_number] => 05702985 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Hermetically sealed ceramic integrated circuit heat dissipating package fabrication method' [patent_app_type] => 1 [patent_app_number] => 8/325719 [patent_app_country] => US [patent_app_date] => 1994-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 7533 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/702/05702985.pdf [firstpage_image] =>[orig_patent_app_number] => 325719 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/325719
Hermetically sealed ceramic integrated circuit heat dissipating package fabrication method Oct 18, 1994 Issued
Array ( [id] => 3656129 [patent_doc_number] => 05622887 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Process for fabricating BiCMOS devices including passive devices' [patent_app_type] => 1 [patent_app_number] => 8/323873 [patent_app_country] => US [patent_app_date] => 1994-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 48 [patent_no_of_words] => 9904 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/622/05622887.pdf [firstpage_image] =>[orig_patent_app_number] => 323873 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/323873
Process for fabricating BiCMOS devices including passive devices Oct 16, 1994 Issued
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