Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3517368 [patent_doc_number] => 05506156 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-09 [patent_title] => 'Method of fabricating bipolar transistor having high speed and MOS transistor having small size' [patent_app_type] => 1 [patent_app_number] => 8/279087 [patent_app_country] => US [patent_app_date] => 1994-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3126 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/506/05506156.pdf [firstpage_image] =>[orig_patent_app_number] => 279087 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/279087
Method of fabricating bipolar transistor having high speed and MOS transistor having small size Jul 21, 1994 Issued
08/273253 ATTACHING HEAT SINKS DIRECTLY TO CHIP CARRIER MODULES USING FLEXIBLE-EPOXY Jul 10, 1994 Abandoned
Array ( [id] => 3423785 [patent_doc_number] => 05459096 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Process for fabricating a semiconductor device using dual planarization layers' [patent_app_type] => 1 [patent_app_number] => 8/270545 [patent_app_country] => US [patent_app_date] => 1994-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3506 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459096.pdf [firstpage_image] =>[orig_patent_app_number] => 270545 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/270545
Process for fabricating a semiconductor device using dual planarization layers Jul 4, 1994 Issued
Array ( [id] => 3410519 [patent_doc_number] => 05461010 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-24 [patent_title] => 'Two step etch back spin-on-glass process for semiconductor planarization' [patent_app_type] => 1 [patent_app_number] => 8/258997 [patent_app_country] => US [patent_app_date] => 1994-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3878 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/461/05461010.pdf [firstpage_image] =>[orig_patent_app_number] => 258997 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/258997
Two step etch back spin-on-glass process for semiconductor planarization Jun 12, 1994 Issued
Array ( [id] => 3427488 [patent_doc_number] => 05462888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'Process for manufacturing semiconductor BICMOS device' [patent_app_type] => 1 [patent_app_number] => 8/254223 [patent_app_country] => US [patent_app_date] => 1994-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3968 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/462/05462888.pdf [firstpage_image] =>[orig_patent_app_number] => 254223 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/254223
Process for manufacturing semiconductor BICMOS device Jun 5, 1994 Issued
Array ( [id] => 3529452 [patent_doc_number] => 05583059 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Fabrication of vertical SiGe base HBT with lateral collector contact on thin SOI' [patent_app_type] => 1 [patent_app_number] => 8/251987 [patent_app_country] => US [patent_app_date] => 1994-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3941 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/583/05583059.pdf [firstpage_image] =>[orig_patent_app_number] => 251987 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/251987
Fabrication of vertical SiGe base HBT with lateral collector contact on thin SOI May 31, 1994 Issued
Array ( [id] => 3663526 [patent_doc_number] => 05668047 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'Method for fabricating InP diffraction grating and distributed feedback laser' [patent_app_type] => 1 [patent_app_number] => 8/251259 [patent_app_country] => US [patent_app_date] => 1994-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1496 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668047.pdf [firstpage_image] =>[orig_patent_app_number] => 251259 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/251259
Method for fabricating InP diffraction grating and distributed feedback laser May 30, 1994 Issued
Array ( [id] => 3493723 [patent_doc_number] => 05508229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-16 [patent_title] => 'Method for forming solder bumps in semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/248409 [patent_app_country] => US [patent_app_date] => 1994-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2667 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/508/05508229.pdf [firstpage_image] =>[orig_patent_app_number] => 248409 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/248409
Method for forming solder bumps in semiconductor devices May 23, 1994 Issued
Array ( [id] => 3521954 [patent_doc_number] => 05489547 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Method of fabricating semiconductor device having polysilicon resistor with low temperature coefficient' [patent_app_type] => 1 [patent_app_number] => 8/247443 [patent_app_country] => US [patent_app_date] => 1994-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3964 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/489/05489547.pdf [firstpage_image] =>[orig_patent_app_number] => 247443 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/247443
Method of fabricating semiconductor device having polysilicon resistor with low temperature coefficient May 22, 1994 Issued
Array ( [id] => 3621188 [patent_doc_number] => 05593902 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Method of making photodiodes for low dark current operation having geometric enhancement' [patent_app_type] => 1 [patent_app_number] => 8/247747 [patent_app_country] => US [patent_app_date] => 1994-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 1651 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/593/05593902.pdf [firstpage_image] =>[orig_patent_app_number] => 247747 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/247747
Method of making photodiodes for low dark current operation having geometric enhancement May 22, 1994 Issued
Array ( [id] => 3574243 [patent_doc_number] => 05523242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Method of manufacturing a BiMOS device' [patent_app_type] => 1 [patent_app_number] => 8/243919 [patent_app_country] => US [patent_app_date] => 1994-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4279 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/523/05523242.pdf [firstpage_image] =>[orig_patent_app_number] => 243919 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/243919
Method of manufacturing a BiMOS device May 16, 1994 Issued
Array ( [id] => 3419265 [patent_doc_number] => 05478764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'Method of producing semiconductor device including Schottky barrier diode incorporating a CVD refractory metal layer' [patent_app_type] => 1 [patent_app_number] => 8/240392 [patent_app_country] => US [patent_app_date] => 1994-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4051 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/478/05478764.pdf [firstpage_image] =>[orig_patent_app_number] => 240392 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/240392
Method of producing semiconductor device including Schottky barrier diode incorporating a CVD refractory metal layer May 9, 1994 Issued
Array ( [id] => 3428339 [patent_doc_number] => 05455195 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-03 [patent_title] => 'Method for obtaining metallurgical stability in integrated circuit conductive bonds' [patent_app_type] => 1 [patent_app_number] => 8/238995 [patent_app_country] => US [patent_app_date] => 1994-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2035 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/455/05455195.pdf [firstpage_image] =>[orig_patent_app_number] => 238995 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/238995
Method for obtaining metallurgical stability in integrated circuit conductive bonds May 5, 1994 Issued
08/239435 LOW VOLTAGE CMOS PROCESS AND DEVICE WITH INDIVIDUALLY ADJUSTABLE LDD SPACERS May 5, 1994 Abandoned
Array ( [id] => 3444038 [patent_doc_number] => 05420053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'Method for manufacturing semiconductor device having bipolar transistor and polycrystalline silicon resistor' [patent_app_type] => 1 [patent_app_number] => 8/237995 [patent_app_country] => US [patent_app_date] => 1994-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 31 [patent_no_of_words] => 4631 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/420/05420053.pdf [firstpage_image] =>[orig_patent_app_number] => 237995 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/237995
Method for manufacturing semiconductor device having bipolar transistor and polycrystalline silicon resistor May 3, 1994 Issued
Array ( [id] => 3444003 [patent_doc_number] => 05420052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'Method of fabricating a semiplanar heterojunction bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/230357 [patent_app_country] => US [patent_app_date] => 1994-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1407 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/420/05420052.pdf [firstpage_image] =>[orig_patent_app_number] => 230357 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/230357
Method of fabricating a semiplanar heterojunction bipolar transistor Apr 18, 1994 Issued
Array ( [id] => 3423885 [patent_doc_number] => 05459103 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Method of forming lead frame with strengthened encapsulation adhesion' [patent_app_type] => 1 [patent_app_number] => 8/228996 [patent_app_country] => US [patent_app_date] => 1994-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3788 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459103.pdf [firstpage_image] =>[orig_patent_app_number] => 228996 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/228996
Method of forming lead frame with strengthened encapsulation adhesion Apr 17, 1994 Issued
Array ( [id] => 2993671 [patent_doc_number] => 05362656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-08 [patent_title] => 'Method of making an electronic assembly having a flexible circuit wrapped around a substrate' [patent_app_type] => 1 [patent_app_number] => 8/228095 [patent_app_country] => US [patent_app_date] => 1994-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1904 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/362/05362656.pdf [firstpage_image] =>[orig_patent_app_number] => 228095 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/228095
Method of making an electronic assembly having a flexible circuit wrapped around a substrate Apr 14, 1994 Issued
Array ( [id] => 3564741 [patent_doc_number] => 05482871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-09 [patent_title] => 'Method for forming a mesa-isolated SOI transistor having a split-process polysilicon gate' [patent_app_type] => 1 [patent_app_number] => 8/228043 [patent_app_country] => US [patent_app_date] => 1994-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4071 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/482/05482871.pdf [firstpage_image] =>[orig_patent_app_number] => 228043 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/228043
Method for forming a mesa-isolated SOI transistor having a split-process polysilicon gate Apr 14, 1994 Issued
Array ( [id] => 3539657 [patent_doc_number] => 05480842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'Method for fabricating thin, strong, and flexible die for smart cards' [patent_app_type] => 1 [patent_app_number] => 8/225687 [patent_app_country] => US [patent_app_date] => 1994-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2927 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/480/05480842.pdf [firstpage_image] =>[orig_patent_app_number] => 225687 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/225687
Method for fabricating thin, strong, and flexible die for smart cards Apr 10, 1994 Issued
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