Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2968145 [patent_doc_number] => 05252081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-12 [patent_title] => 'Plug for use with self regulating cable' [patent_app_type] => 1 [patent_app_number] => 8/103363 [patent_app_country] => US [patent_app_date] => 1993-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2575 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/252/05252081.pdf [firstpage_image] =>[orig_patent_app_number] => 103363 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/103363
Method for making cooling structures for directly cooling an active layer of a semiconductor chip Aug 8, 1993 Issued
Array ( [id] => 2968145 [patent_doc_number] => 05252081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-12 [patent_title] => 'Plug for use with self regulating cable' [patent_app_type] => 1 [patent_app_number] => 8/103363 [patent_app_country] => US [patent_app_date] => 1993-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2575 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/252/05252081.pdf [firstpage_image] =>[orig_patent_app_number] => 103363 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/103363
Method for making cooling structures for directly cooling an active layer of a semiconductor chip Aug 8, 1993 Issued
Array ( [id] => 3428416 [patent_doc_number] => 05455200 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-03 [patent_title] => 'Method for making a lead-on-chip semiconductor device having peripheral bond pads' [patent_app_type] => 1 [patent_app_number] => 8/097505 [patent_app_country] => US [patent_app_date] => 1993-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3362 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/455/05455200.pdf [firstpage_image] =>[orig_patent_app_number] => 097505 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/097505
Method for making a lead-on-chip semiconductor device having peripheral bond pads Jul 26, 1993 Issued
Array ( [id] => 3482515 [patent_doc_number] => 05474640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'Apparatus for marking a substrate using ionized gas' [patent_app_type] => 1 [patent_app_number] => 8/094653 [patent_app_country] => US [patent_app_date] => 1993-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1895 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/474/05474640.pdf [firstpage_image] =>[orig_patent_app_number] => 094653 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/094653
Apparatus for marking a substrate using ionized gas Jul 18, 1993 Issued
Array ( [id] => 3419225 [patent_doc_number] => 05478761 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'Method of producing semiconductor device having first and second type field effect transistors' [patent_app_type] => 1 [patent_app_number] => 8/086449 [patent_app_country] => US [patent_app_date] => 1993-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 39 [patent_no_of_words] => 6746 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/478/05478761.pdf [firstpage_image] =>[orig_patent_app_number] => 086449 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/086449
Method of producing semiconductor device having first and second type field effect transistors Jul 5, 1993 Issued
08/079301 TECHNIQUES FOR MOUNTING SEMICONDUCTOR DIES IN DIE-RECEIVING AREAS HAVING A SHAPE DIFFERING FROM THAT OF THE DIE Jun 17, 1993 Pending
Array ( [id] => 3029157 [patent_doc_number] => 05342794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-30 [patent_title] => 'Method for forming laterally graded deposit-type emitter for bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/073843 [patent_app_country] => US [patent_app_date] => 1993-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5004 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/342/05342794.pdf [firstpage_image] =>[orig_patent_app_number] => 073843 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/073843
Method for forming laterally graded deposit-type emitter for bipolar transistor Jun 6, 1993 Issued
Array ( [id] => 3064884 [patent_doc_number] => 05294558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-15 [patent_title] => 'Method of making double-self-aligned bipolar transistor structure' [patent_app_type] => 1 [patent_app_number] => 8/069337 [patent_app_country] => US [patent_app_date] => 1993-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4400 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 502 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/294/05294558.pdf [firstpage_image] =>[orig_patent_app_number] => 069337 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/069337
Method of making double-self-aligned bipolar transistor structure May 31, 1993 Issued
08/069083 LOCAL INTERCONNECT STRUCTURE May 27, 1993 Pending
Array ( [id] => 4152208 [patent_doc_number] => 06124180 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'BiCMOS process for counter doped collector' [patent_app_type] => 1 [patent_app_number] => 8/066618 [patent_app_country] => US [patent_app_date] => 1993-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2122 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124180.pdf [firstpage_image] =>[orig_patent_app_number] => 066618 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/066618
BiCMOS process for counter doped collector May 23, 1993 Issued
Array ( [id] => 3038471 [patent_doc_number] => 05376562 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'Method for forming vertical transistor structures having bipolar and MOS devices' [patent_app_type] => 1 [patent_app_number] => 8/065419 [patent_app_country] => US [patent_app_date] => 1993-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5452 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/376/05376562.pdf [firstpage_image] =>[orig_patent_app_number] => 065419 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/065419
Method for forming vertical transistor structures having bipolar and MOS devices May 23, 1993 Issued
08/058347 ZIG-ZAG LINEAR ARRANGEMENT FOR INTERIOR BOND PADS May 4, 1993 Pending
Array ( [id] => 3487250 [patent_doc_number] => 05474958 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'Method for making semiconductor device having no die supporting surface' [patent_app_type] => 1 [patent_app_number] => 8/055863 [patent_app_country] => US [patent_app_date] => 1993-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 26 [patent_no_of_words] => 7059 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/474/05474958.pdf [firstpage_image] =>[orig_patent_app_number] => 055863 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/055863
Method for making semiconductor device having no die supporting surface May 3, 1993 Issued
Array ( [id] => 3460920 [patent_doc_number] => 05468666 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-21 [patent_title] => 'Using a change in doping of poly gate to permit placing both high voltage and low voltage transistors on the same chip' [patent_app_type] => 1 [patent_app_number] => 8/055999 [patent_app_country] => US [patent_app_date] => 1993-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 3982 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/468/05468666.pdf [firstpage_image] =>[orig_patent_app_number] => 055999 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/055999
Using a change in doping of poly gate to permit placing both high voltage and low voltage transistors on the same chip Apr 28, 1993 Issued
Array ( [id] => 3592308 [patent_doc_number] => 05488003 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-30 [patent_title] => 'Method of making emitter trench BiCMOS using integrated dual layer emitter mask' [patent_app_type] => 1 [patent_app_number] => 8/040673 [patent_app_country] => US [patent_app_date] => 1993-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 6344 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/488/05488003.pdf [firstpage_image] =>[orig_patent_app_number] => 040673 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/040673
Method of making emitter trench BiCMOS using integrated dual layer emitter mask Mar 30, 1993 Issued
Array ( [id] => 3085956 [patent_doc_number] => 05278082 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-11 [patent_title] => 'Method for electrically connecting an electrode and impurity-diffused layer formed on a semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 8/036621 [patent_app_country] => US [patent_app_date] => 1993-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 3800 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/278/05278082.pdf [firstpage_image] =>[orig_patent_app_number] => 036621 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/036621
Method for electrically connecting an electrode and impurity-diffused layer formed on a semiconductor substrate Mar 23, 1993 Issued
Array ( [id] => 3077425 [patent_doc_number] => 05320975 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-14 [patent_title] => 'Method of forming thin film pseudo-planar FET devices and structures resulting therefrom' [patent_app_type] => 1 [patent_app_number] => 8/034325 [patent_app_country] => US [patent_app_date] => 1993-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 33 [patent_no_of_words] => 8414 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/320/05320975.pdf [firstpage_image] =>[orig_patent_app_number] => 034325 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/034325
Method of forming thin film pseudo-planar FET devices and structures resulting therefrom Mar 21, 1993 Issued
Array ( [id] => 3417387 [patent_doc_number] => 05434095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-18 [patent_title] => 'Method for controlling electrical breakdown in semiconductor power devices' [patent_app_type] => 1 [patent_app_number] => 8/030797 [patent_app_country] => US [patent_app_date] => 1993-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2816 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/434/05434095.pdf [firstpage_image] =>[orig_patent_app_number] => 030797 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/030797
Method for controlling electrical breakdown in semiconductor power devices Mar 11, 1993 Issued
Array ( [id] => 3474659 [patent_doc_number] => 05427984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-27 [patent_title] => 'Method of making a cooling package for a semiconductor chip' [patent_app_type] => 1 [patent_app_number] => 8/024129 [patent_app_country] => US [patent_app_date] => 1993-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 1768 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/427/05427984.pdf [firstpage_image] =>[orig_patent_app_number] => 024129 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/024129
Method of making a cooling package for a semiconductor chip Feb 28, 1993 Issued
Array ( [id] => 3423604 [patent_doc_number] => 05459083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Method for making BIMOS device having a bipolar transistor and a MOS triggering transistor' [patent_app_type] => 1 [patent_app_number] => 8/024719 [patent_app_country] => US [patent_app_date] => 1993-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 5811 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459083.pdf [firstpage_image] =>[orig_patent_app_number] => 024719 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/024719
Method for making BIMOS device having a bipolar transistor and a MOS triggering transistor Feb 28, 1993 Issued
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