Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
08/022400 METHOD OF PRODUCING SEMICONDUCTOR DEVICE INCLUDING SCHOTTKY BARRIER DIODE Feb 23, 1993 Abandoned
Array ( [id] => 3415243 [patent_doc_number] => 05393677 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-28 [patent_title] => 'Method of optimizing wells for PMOS and bipolar to yield an improved BICMOS process' [patent_app_type] => 1 [patent_app_number] => 8/020234 [patent_app_country] => US [patent_app_date] => 1993-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1750 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/393/05393677.pdf [firstpage_image] =>[orig_patent_app_number] => 020234 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/020234
Method of optimizing wells for PMOS and bipolar to yield an improved BICMOS process Feb 18, 1993 Issued
08/018354 GIGAOHM LOAD RESISTOR FOR BICMOS PROCESS Feb 15, 1993 Abandoned
Array ( [id] => 3012246 [patent_doc_number] => 05332683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-26 [patent_title] => 'Method of manufacturing semiconductor device having elements isolated by trench' [patent_app_type] => 1 [patent_app_number] => 8/015672 [patent_app_country] => US [patent_app_date] => 1993-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3230 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/332/05332683.pdf [firstpage_image] =>[orig_patent_app_number] => 015672 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/015672
Method of manufacturing semiconductor device having elements isolated by trench Feb 8, 1993 Issued
Array ( [id] => 3017679 [patent_doc_number] => 05288654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-22 [patent_title] => 'Method of making a mushroom-shaped gate electrode of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/014857 [patent_app_country] => US [patent_app_date] => 1993-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 3543 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/288/05288654.pdf [firstpage_image] =>[orig_patent_app_number] => 014857 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/014857
Method of making a mushroom-shaped gate electrode of semiconductor device Feb 7, 1993 Issued
08/014421 STRUCTURE OF SEMICONDUCTOR DEVICE IMPLEMENTED BY COMPLEMENTARY INVERTER CIRCUIT AND PROCESS OF FABRICATION THEREOF Feb 4, 1993 Abandoned
Array ( [id] => 2968145 [patent_doc_number] => 05252081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-12 [patent_title] => 'Plug for use with self regulating cable' [patent_app_type] => 1 [patent_app_number] => 8/103363 [patent_app_country] => US [patent_app_date] => 1993-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2575 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/252/05252081.pdf [firstpage_image] =>[orig_patent_app_number] => 103363 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/103363
Plug for use with self regulating cable Feb 3, 1993 Issued
Array ( [id] => 2968145 [patent_doc_number] => 05252081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-12 [patent_title] => 'Plug for use with self regulating cable' [patent_app_type] => 1 [patent_app_number] => 8/103363 [patent_app_country] => US [patent_app_date] => 1993-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2575 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/252/05252081.pdf [firstpage_image] =>[orig_patent_app_number] => 103363 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/103363
Plug for use with self regulating cable Feb 3, 1993 Issued
Array ( [id] => 3551981 [patent_doc_number] => 05492844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-20 [patent_title] => 'Method of manufacturing increased conductivity base contact/feeders with self-aligned structures' [patent_app_type] => 1 [patent_app_number] => 8/011159 [patent_app_country] => US [patent_app_date] => 1993-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 20 [patent_no_of_words] => 2225 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/492/05492844.pdf [firstpage_image] =>[orig_patent_app_number] => 011159 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/011159
Method of manufacturing increased conductivity base contact/feeders with self-aligned structures Jan 28, 1993 Issued
Array ( [id] => 3421741 [patent_doc_number] => 05389552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Transistors having bases with different shape top surfaces' [patent_app_type] => 1 [patent_app_number] => 8/010919 [patent_app_country] => US [patent_app_date] => 1993-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5151 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/389/05389552.pdf [firstpage_image] =>[orig_patent_app_number] => 010919 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/010919
Transistors having bases with different shape top surfaces Jan 28, 1993 Issued
08/011019 METHOD OF MAKING BIPOLAR TRANSISTOR HAVING A HIGH RATIO OF EMITTER TO BASE AREA Jan 28, 1993 Abandoned
Array ( [id] => 3093630 [patent_doc_number] => 05298440 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-29 [patent_title] => 'Method of fabrication of transistor device with increased breakdown voltage' [patent_app_type] => 1 [patent_app_number] => 8/008054 [patent_app_country] => US [patent_app_date] => 1993-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 29 [patent_no_of_words] => 4454 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/298/05298440.pdf [firstpage_image] =>[orig_patent_app_number] => 008054 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/008054
Method of fabrication of transistor device with increased breakdown voltage Jan 21, 1993 Issued
Array ( [id] => 3032531 [patent_doc_number] => 05328859 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-12 [patent_title] => 'Method of making high voltage PNP bipolar transistor in CMOS' [patent_app_type] => 1 [patent_app_number] => 8/000357 [patent_app_country] => US [patent_app_date] => 1993-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 3120 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/328/05328859.pdf [firstpage_image] =>[orig_patent_app_number] => 000357 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/000357
Method of making high voltage PNP bipolar transistor in CMOS Jan 3, 1993 Issued
Array ( [id] => 3424786 [patent_doc_number] => 05422299 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-06 [patent_title] => 'Method of forming single crystalline electrical isolated wells' [patent_app_type] => 1 [patent_app_number] => 8/000802 [patent_app_country] => US [patent_app_date] => 1993-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 84 [patent_no_of_words] => 13943 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/422/05422299.pdf [firstpage_image] =>[orig_patent_app_number] => 000802 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/000802
Method of forming single crystalline electrical isolated wells Jan 3, 1993 Issued
Array ( [id] => 3038878 [patent_doc_number] => 05376584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'Process of making pad structure for solder ball limiting metallurgy having reduced edge stress' [patent_app_type] => 1 [patent_app_number] => 7/998982 [patent_app_country] => US [patent_app_date] => 1992-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2167 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/376/05376584.pdf [firstpage_image] =>[orig_patent_app_number] => 998982 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/998982
Process of making pad structure for solder ball limiting metallurgy having reduced edge stress Dec 30, 1992 Issued
Array ( [id] => 3476044 [patent_doc_number] => 05432103 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-11 [patent_title] => 'Method of making semiconductor ROM cell programmed using source mask' [patent_app_type] => 1 [patent_app_number] => 7/996807 [patent_app_country] => US [patent_app_date] => 1992-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 3750 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/432/05432103.pdf [firstpage_image] =>[orig_patent_app_number] => 996807 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/996807
Method of making semiconductor ROM cell programmed using source mask Dec 22, 1992 Issued
Array ( [id] => 2985123 [patent_doc_number] => 05266505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-30 [patent_title] => 'Image reversal process for self-aligned implants in planar epitaxial-base bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 7/994743 [patent_app_country] => US [patent_app_date] => 1992-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 15 [patent_no_of_words] => 2312 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/266/05266505.pdf [firstpage_image] =>[orig_patent_app_number] => 994743 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/994743
Image reversal process for self-aligned implants in planar epitaxial-base bipolar transistors Dec 21, 1992 Issued
Array ( [id] => 3482231 [patent_doc_number] => 05445995 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Method for manufacturing plastic-encapsulated semiconductor devices with exposed metal heat sink' [patent_app_type] => 1 [patent_app_number] => 7/994421 [patent_app_country] => US [patent_app_date] => 1992-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 2161 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/445/05445995.pdf [firstpage_image] =>[orig_patent_app_number] => 994421 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/994421
Method for manufacturing plastic-encapsulated semiconductor devices with exposed metal heat sink Dec 20, 1992 Issued
Array ( [id] => 3017642 [patent_doc_number] => 05288652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-22 [patent_title] => 'BICMOS-compatible method for creating a bipolar transistor with laterally graded emitter structure' [patent_app_type] => 1 [patent_app_number] => 7/993229 [patent_app_country] => US [patent_app_date] => 1992-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3524 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/288/05288652.pdf [firstpage_image] =>[orig_patent_app_number] => 993229 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/993229
BICMOS-compatible method for creating a bipolar transistor with laterally graded emitter structure Dec 17, 1992 Issued
Array ( [id] => 3487105 [patent_doc_number] => 05474948 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'Method of making semiconductor device having polysilicon resistance element' [patent_app_type] => 1 [patent_app_number] => 7/994095 [patent_app_country] => US [patent_app_date] => 1992-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2973 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/474/05474948.pdf [firstpage_image] =>[orig_patent_app_number] => 994095 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/994095
Method of making semiconductor device having polysilicon resistance element Dec 17, 1992 Issued
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