Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2989082 [patent_doc_number] => 05346840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-13 [patent_title] => 'Method of producing heterojunction bipolar transistor having narrow band gap base type' [patent_app_type] => 1 [patent_app_number] => 7/986294 [patent_app_country] => US [patent_app_date] => 1992-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3266 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/346/05346840.pdf [firstpage_image] =>[orig_patent_app_number] => 986294 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/986294
Method of producing heterojunction bipolar transistor having narrow band gap base type Dec 6, 1992 Issued
Array ( [id] => 3049482 [patent_doc_number] => 05306649 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-26 [patent_title] => 'Method for producing a fully walled emitter-base structure in a bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 7/982226 [patent_app_country] => US [patent_app_date] => 1992-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 34 [patent_no_of_words] => 6992 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/306/05306649.pdf [firstpage_image] =>[orig_patent_app_number] => 982226 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/982226
Method for producing a fully walled emitter-base structure in a bipolar transistor Nov 24, 1992 Issued
Array ( [id] => 3049051 [patent_doc_number] => 05324673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-28 [patent_title] => 'Method of formation of vertical transistor' [patent_app_type] => 1 [patent_app_number] => 7/979073 [patent_app_country] => US [patent_app_date] => 1992-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 3879 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/324/05324673.pdf [firstpage_image] =>[orig_patent_app_number] => 979073 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/979073
Method of formation of vertical transistor Nov 18, 1992 Issued
07/969605 REDUCING JUNCTION CAPACITANCE AND INCREASING CURRENT GAIN IN COLLECTOR-UP BIPOLAR TRANSISTORS Oct 29, 1992 Abandoned
Array ( [id] => 3033892 [patent_doc_number] => 05300451 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Process for forming a buried drain or collector region in monolithic semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 7/967553 [patent_app_country] => US [patent_app_date] => 1992-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 28 [patent_no_of_words] => 3159 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/300/05300451.pdf [firstpage_image] =>[orig_patent_app_number] => 967553 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/967553
Process for forming a buried drain or collector region in monolithic semiconductor devices Oct 26, 1992 Issued
Array ( [id] => 3509492 [patent_doc_number] => 05587326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'Method of forming bipolar junction transistor of epitaxial planar type' [patent_app_type] => 1 [patent_app_number] => 7/965027 [patent_app_country] => US [patent_app_date] => 1992-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3010 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/587/05587326.pdf [firstpage_image] =>[orig_patent_app_number] => 965027 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/965027
Method of forming bipolar junction transistor of epitaxial planar type Oct 22, 1992 Issued
Array ( [id] => 3049033 [patent_doc_number] => 05324672 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-28 [patent_title] => 'Manufacturing method for bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 7/966085 [patent_app_country] => US [patent_app_date] => 1992-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 47 [patent_no_of_words] => 18160 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/324/05324672.pdf [firstpage_image] =>[orig_patent_app_number] => 966085 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/966085
Manufacturing method for bipolar transistor Oct 22, 1992 Issued
Array ( [id] => 3014718 [patent_doc_number] => 05340755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Method of making planar heterobipolar transistor having trenched isolation of the collector terminal' [patent_app_type] => 1 [patent_app_number] => 7/912271 [patent_app_country] => US [patent_app_date] => 1992-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 5611 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/340/05340755.pdf [firstpage_image] =>[orig_patent_app_number] => 912271 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/912271
Method of making planar heterobipolar transistor having trenched isolation of the collector terminal Oct 12, 1992 Issued
Array ( [id] => 3032514 [patent_doc_number] => 05328858 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-12 [patent_title] => 'Method for producing the bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 7/956865 [patent_app_country] => US [patent_app_date] => 1992-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1715 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/328/05328858.pdf [firstpage_image] =>[orig_patent_app_number] => 956865 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/956865
Method for producing the bipolar transistor Oct 4, 1992 Issued
Array ( [id] => 3017157 [patent_doc_number] => 05302535 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-12 [patent_title] => 'Method of manufacturing high speed bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 7/947257 [patent_app_country] => US [patent_app_date] => 1992-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 8545 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/302/05302535.pdf [firstpage_image] =>[orig_patent_app_number] => 947257 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/947257
Method of manufacturing high speed bipolar transistor Sep 17, 1992 Issued
Array ( [id] => 2942085 [patent_doc_number] => 05254507 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-19 [patent_title] => 'Semi-insulating InP single crystals, semiconductor devices having substrates of the crystals and processes for producing the same' [patent_app_type] => 1 [patent_app_number] => 7/943686 [patent_app_country] => US [patent_app_date] => 1992-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4418 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/254/05254507.pdf [firstpage_image] =>[orig_patent_app_number] => 943686 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/943686
Semi-insulating InP single crystals, semiconductor devices having substrates of the crystals and processes for producing the same Sep 10, 1992 Issued
Array ( [id] => 3052121 [patent_doc_number] => 05344786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-06 [patent_title] => 'Method of fabricating self-aligned heterojunction bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 7/942474 [patent_app_country] => US [patent_app_date] => 1992-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2252 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/344/05344786.pdf [firstpage_image] =>[orig_patent_app_number] => 942474 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/942474
Method of fabricating self-aligned heterojunction bipolar transistors Sep 8, 1992 Issued
Array ( [id] => 3459881 [patent_doc_number] => 05391503 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Method of forming a stacked semiconductor device wherein semiconductor layers and insulating films are sequentially stacked and forming openings through such films and etchings using one of the insulating films as a mask' [patent_app_type] => 1 [patent_app_number] => 7/944261 [patent_app_country] => US [patent_app_date] => 1992-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 37 [patent_no_of_words] => 9598 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/391/05391503.pdf [firstpage_image] =>[orig_patent_app_number] => 944261 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/944261
Method of forming a stacked semiconductor device wherein semiconductor layers and insulating films are sequentially stacked and forming openings through such films and etchings using one of the insulating films as a mask Sep 3, 1992 Issued
Array ( [id] => 3032474 [patent_doc_number] => 05328856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-12 [patent_title] => 'Method for producing bipolar transistors having polysilicon contacted terminals' [patent_app_type] => 1 [patent_app_number] => 7/937329 [patent_app_country] => US [patent_app_date] => 1992-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2369 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/328/05328856.pdf [firstpage_image] =>[orig_patent_app_number] => 937329 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/937329
Method for producing bipolar transistors having polysilicon contacted terminals Aug 26, 1992 Issued
Array ( [id] => 3112939 [patent_doc_number] => 05409843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'Method of producing a semiconductor device by forming contacts after flowing a glass layer' [patent_app_type] => 1 [patent_app_number] => 7/933584 [patent_app_country] => US [patent_app_date] => 1992-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3165 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/409/05409843.pdf [firstpage_image] =>[orig_patent_app_number] => 933584 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/933584
Method of producing a semiconductor device by forming contacts after flowing a glass layer Aug 23, 1992 Issued
07/933249 VERTICAL-TYPE DOUBLE DIFFUSED MOSFET AND METHOD OF FABRICATING THE SAME Aug 20, 1992 Abandoned
Array ( [id] => 2935132 [patent_doc_number] => 05260226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-09 [patent_title] => 'Semiconductor device having different impurity concentration wells' [patent_app_type] => 1 [patent_app_number] => 7/928527 [patent_app_country] => US [patent_app_date] => 1992-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 34 [patent_no_of_words] => 4610 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/260/05260226.pdf [firstpage_image] =>[orig_patent_app_number] => 928527 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/928527
Semiconductor device having different impurity concentration wells Aug 11, 1992 Issued
Array ( [id] => 2893432 [patent_doc_number] => 05240882 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-31 [patent_title] => 'Process and apparatus for making discrete type substrates by re-slicing a wafer' [patent_app_type] => 1 [patent_app_number] => 7/921466 [patent_app_country] => US [patent_app_date] => 1992-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 4203 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/240/05240882.pdf [firstpage_image] =>[orig_patent_app_number] => 921466 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/921466
Process and apparatus for making discrete type substrates by re-slicing a wafer Jul 27, 1992 Issued
Array ( [id] => 3049795 [patent_doc_number] => 05283200 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-01 [patent_title] => 'Method of fabricating complementary semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/918683 [patent_app_country] => US [patent_app_date] => 1992-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1469 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/283/05283200.pdf [firstpage_image] =>[orig_patent_app_number] => 918683 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/918683
Method of fabricating complementary semiconductor device Jul 26, 1992 Issued
Array ( [id] => 3017626 [patent_doc_number] => 05288651 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-22 [patent_title] => 'Method of making semiconductor integrated circuit device including bipolar transistors, MOS FETs and CCD' [patent_app_type] => 1 [patent_app_number] => 7/914587 [patent_app_country] => US [patent_app_date] => 1992-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2893 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/288/05288651.pdf [firstpage_image] =>[orig_patent_app_number] => 914587 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/914587
Method of making semiconductor integrated circuit device including bipolar transistors, MOS FETs and CCD Jul 19, 1992 Issued
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