| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3077345
[patent_doc_number] => 05320971
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-06-14
[patent_title] => 'Process for obtaining high barrier Schottky diode and local interconnect'
[patent_app_type] => 1
[patent_app_number] => 7/908761
[patent_app_country] => US
[patent_app_date] => 1992-07-01
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[pdf_file] => patents/05/320/05320971.pdf
[firstpage_image] =>[orig_patent_app_number] => 908761
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/908761 | Process for obtaining high barrier Schottky diode and local interconnect | Jun 30, 1992 | Issued |
Array
(
[id] => 3421909
[patent_doc_number] => 05389564
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-14
[patent_title] => 'Method of forming a GaAs FET having etched ohmic contacts'
[patent_app_type] => 1
[patent_app_number] => 7/902245
[patent_app_country] => US
[patent_app_date] => 1992-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/389/05389564.pdf
[firstpage_image] =>[orig_patent_app_number] => 902245
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/902245 | Method of forming a GaAs FET having etched ohmic contacts | Jun 21, 1992 | Issued |
| 07/900399 | METHOD OF MAKING MULTILAYER BASE HETEROJUNCTION DEVICE | Jun 17, 1992 | Abandoned |
Array
(
[id] => 4116529
[patent_doc_number] => 06071767
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'High performance/high density BICMOS process'
[patent_app_type] => 1
[patent_app_number] => 7/900528
[patent_app_country] => US
[patent_app_date] => 1992-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 4211
[patent_no_of_claims] => 19
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[patent_maintenance] => 1
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[pdf_file] => patents/06/071/06071767.pdf
[firstpage_image] =>[orig_patent_app_number] => 900528
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/900528 | High performance/high density BICMOS process | Jun 16, 1992 | Issued |
Array
(
[id] => 2985956
[patent_doc_number] => 05212102
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-05-18
[patent_title] => 'Method of making polysilicon Schottky clamped transistor and vertical fuse devices'
[patent_app_type] => 1
[patent_app_number] => 7/894403
[patent_app_country] => US
[patent_app_date] => 1992-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 4854
[patent_no_of_claims] => 11
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[pdf_file] => patents/05/212/05212102.pdf
[firstpage_image] =>[orig_patent_app_number] => 894403
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/894403 | Method of making polysilicon Schottky clamped transistor and vertical fuse devices | Jun 4, 1992 | Issued |
Array
(
[id] => 3415331
[patent_doc_number] => 05393683
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-28
[patent_title] => 'Method of making semiconductor devices having two-layer gate structure'
[patent_app_type] => 1
[patent_app_number] => 7/887785
[patent_app_country] => US
[patent_app_date] => 1992-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2236
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[pdf_file] => patents/05/393/05393683.pdf
[firstpage_image] =>[orig_patent_app_number] => 887785
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/887785 | Method of making semiconductor devices having two-layer gate structure | May 25, 1992 | Issued |
Array
(
[id] => 2957971
[patent_doc_number] => 05198373
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-30
[patent_title] => 'Process for fabricating a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 7/886399
[patent_app_country] => US
[patent_app_date] => 1992-05-21
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[pdf_file] => patents/05/198/05198373.pdf
[firstpage_image] =>[orig_patent_app_number] => 886399
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/886399 | Process for fabricating a semiconductor device | May 20, 1992 | Issued |
Array
(
[id] => 2883911
[patent_doc_number] => 05268323
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-12-07
[patent_title] => 'Semiconductor array and method for its manufacture'
[patent_app_type] => 1
[patent_app_number] => 7/884187
[patent_app_country] => US
[patent_app_date] => 1992-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/268/05268323.pdf
[firstpage_image] =>[orig_patent_app_number] => 884187
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/884187 | Semiconductor array and method for its manufacture | May 17, 1992 | Issued |
Array
(
[id] => 2948444
[patent_doc_number] => 05262345
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-16
[patent_title] => 'Complimentary bipolar/CMOS fabrication method'
[patent_app_type] => 1
[patent_app_number] => 7/883931
[patent_app_country] => US
[patent_app_date] => 1992-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 3646
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 195
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/262/05262345.pdf
[firstpage_image] =>[orig_patent_app_number] => 883931
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/883931 | Complimentary bipolar/CMOS fabrication method | May 14, 1992 | Issued |
| 07/883331 | SEMICONDUCTOR DEVICE HAVING FIRST AND SECOND TYPE FIELD EFFECT TRANSISTORS AND METHOD OF PRODUCING THE SAME | May 13, 1992 | Abandoned |
Array
(
[id] => 2975016
[patent_doc_number] => 05256589
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-26
[patent_title] => 'Method of improving the flatness of wiring layer'
[patent_app_type] => 1
[patent_app_number] => 7/880555
[patent_app_country] => US
[patent_app_date] => 1992-05-08
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[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/05/256/05256589.pdf
[firstpage_image] =>[orig_patent_app_number] => 880555
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/880555 | Method of improving the flatness of wiring layer | May 7, 1992 | Issued |
Array
(
[id] => 3073868
[patent_doc_number] => 05296409
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-22
[patent_title] => 'Method of making n-channel and p-channel junction field-effect transistors and CMOS transistors using a CMOS or bipolar/CMOS process'
[patent_app_type] => 1
[patent_app_number] => 7/880677
[patent_app_country] => US
[patent_app_date] => 1992-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_no_of_words] => 9078
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[pdf_file] => patents/05/296/05296409.pdf
[firstpage_image] =>[orig_patent_app_number] => 880677
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/880677 | Method of making n-channel and p-channel junction field-effect transistors and CMOS transistors using a CMOS or bipolar/CMOS process | May 7, 1992 | Issued |
| 07/881309 | BICMOS PROCESS FOR COUNTER DOPED COLLECTOR | May 6, 1992 | Abandoned |
Array
(
[id] => 2918175
[patent_doc_number] => 05234846
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-10
[patent_title] => 'Method of making bipolar transistor with reduced topography'
[patent_app_type] => 1
[patent_app_number] => 7/876597
[patent_app_country] => US
[patent_app_date] => 1992-04-30
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[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/234/05234846.pdf
[firstpage_image] =>[orig_patent_app_number] => 876597
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/876597 | Method of making bipolar transistor with reduced topography | Apr 29, 1992 | Issued |
Array
(
[id] => 2931309
[patent_doc_number] => 05188972
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-02-23
[patent_title] => 'Method for making bipolar transistor by self-aligning the emitter to the base contact diffusion'
[patent_app_type] => 1
[patent_app_number] => 7/875239
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[patent_app_date] => 1992-04-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/875239 | Method for making bipolar transistor by self-aligning the emitter to the base contact diffusion | Apr 27, 1992 | Issued |
Array
(
[id] => 3045533
[patent_doc_number] => 05304501
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-19
[patent_title] => 'BiCMOS process with low base recombination current bipolar transistors'
[patent_app_type] => 1
[patent_app_number] => 7/873484
[patent_app_country] => US
[patent_app_date] => 1992-04-22
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[pdf_file] => patents/05/304/05304501.pdf
[firstpage_image] =>[orig_patent_app_number] => 873484
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/873484 | BiCMOS process with low base recombination current bipolar transistors | Apr 21, 1992 | Issued |
Array
(
[id] => 2931273
[patent_doc_number] => 05188970
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-02-23
[patent_title] => 'Method for forming an infrared detector having a refractory metal'
[patent_app_type] => 1
[patent_app_number] => 7/865595
[patent_app_country] => US
[patent_app_date] => 1992-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/05/188/05188970.pdf
[firstpage_image] =>[orig_patent_app_number] => 865595
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/865595 | Method for forming an infrared detector having a refractory metal | Apr 8, 1992 | Issued |
Array
(
[id] => 3091061
[patent_doc_number] => 05312772
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-17
[patent_title] => 'Method of manufacturing interconnect metallization comprising metal nitride and silicide'
[patent_app_type] => 1
[patent_app_number] => 7/863462
[patent_app_country] => US
[patent_app_date] => 1992-04-01
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/312/05312772.pdf
[firstpage_image] =>[orig_patent_app_number] => 863462
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/863462 | Method of manufacturing interconnect metallization comprising metal nitride and silicide | Mar 31, 1992 | Issued |
Array
(
[id] => 2918152
[patent_doc_number] => 05234845
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-10
[patent_title] => 'Method of manufacturing semiconductor IC using selective poly and EPI silicon growth'
[patent_app_type] => 1
[patent_app_number] => 7/859789
[patent_app_country] => US
[patent_app_date] => 1992-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => patents/05/234/05234845.pdf
[firstpage_image] =>[orig_patent_app_number] => 859789
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/859789 | Method of manufacturing semiconductor IC using selective poly and EPI silicon growth | Mar 29, 1992 | Issued |
Array
(
[id] => 2877496
[patent_doc_number] => 05185275
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-02-09
[patent_title] => 'Snap-back preventing method for high voltage MOSFET'
[patent_app_type] => 1
[patent_app_number] => 7/860619
[patent_app_country] => US
[patent_app_date] => 1992-03-30
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/185/05185275.pdf
[firstpage_image] =>[orig_patent_app_number] => 860619
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/860619 | Snap-back preventing method for high voltage MOSFET | Mar 29, 1992 | Issued |