Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
07/828745 METHOD OF MAKING COMPLEMENTARY BIPOLAR POLYSILICON EMITTER DEVICES Jan 30, 1992 Abandoned
Array ( [id] => 3009358 [patent_doc_number] => 05281545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-25 [patent_title] => 'Processes for manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/827899 [patent_app_country] => US [patent_app_date] => 1992-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 3670 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/281/05281545.pdf [firstpage_image] =>[orig_patent_app_number] => 827899 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/827899
Processes for manufacturing a semiconductor device Jan 29, 1992 Issued
Array ( [id] => 2920891 [patent_doc_number] => 05192697 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-09 [patent_title] => 'SOG curing by ion implantation' [patent_app_type] => 1 [patent_app_number] => 7/826115 [patent_app_country] => US [patent_app_date] => 1992-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2786 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/192/05192697.pdf [firstpage_image] =>[orig_patent_app_number] => 826115 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/826115
SOG curing by ion implantation Jan 26, 1992 Issued
Array ( [id] => 2953210 [patent_doc_number] => 05231040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-27 [patent_title] => 'Method of making a field effect transistor' [patent_app_type] => 1 [patent_app_number] => 7/825293 [patent_app_country] => US [patent_app_date] => 1992-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 18 [patent_no_of_words] => 2477 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/231/05231040.pdf [firstpage_image] =>[orig_patent_app_number] => 825293 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/825293
Method of making a field effect transistor Jan 22, 1992 Issued
Array ( [id] => 3049014 [patent_doc_number] => 05324671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-28 [patent_title] => 'Method of fabrication an integrated circuit including bipolar and field effect devices' [patent_app_type] => 1 [patent_app_number] => 7/824429 [patent_app_country] => US [patent_app_date] => 1992-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3352 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/324/05324671.pdf [firstpage_image] =>[orig_patent_app_number] => 824429 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/824429
Method of fabrication an integrated circuit including bipolar and field effect devices Jan 22, 1992 Issued
Array ( [id] => 2909508 [patent_doc_number] => 05227327 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-13 [patent_title] => 'Method for making high impedance pull-up and pull-down input protection resistors for active integrated circuits' [patent_app_type] => 1 [patent_app_number] => 7/819253 [patent_app_country] => US [patent_app_date] => 1992-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 3163 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/227/05227327.pdf [firstpage_image] =>[orig_patent_app_number] => 819253 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/819253
Method for making high impedance pull-up and pull-down input protection resistors for active integrated circuits Jan 9, 1992 Issued
Array ( [id] => 2874880 [patent_doc_number] => 05158896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-27 [patent_title] => 'Method for fabricating group III-V heterostructure devices having self-aligned graded contact diffusion regions' [patent_app_type] => 1 [patent_app_number] => 7/819093 [patent_app_country] => US [patent_app_date] => 1992-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 3281 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/158/05158896.pdf [firstpage_image] =>[orig_patent_app_number] => 819093 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/819093
Method for fabricating group III-V heterostructure devices having self-aligned graded contact diffusion regions Jan 8, 1992 Issued
Array ( [id] => 3009340 [patent_doc_number] => 05281544 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-25 [patent_title] => 'Method of manufacturing planar type polar transistors and combination bipolar/MIS type transistors' [patent_app_type] => 1 [patent_app_number] => 7/818717 [patent_app_country] => US [patent_app_date] => 1992-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 47 [patent_no_of_words] => 7489 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/281/05281544.pdf [firstpage_image] =>[orig_patent_app_number] => 818717 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/818717
Method of manufacturing planar type polar transistors and combination bipolar/MIS type transistors Jan 8, 1992 Issued
Array ( [id] => 2932871 [patent_doc_number] => 05229313 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-20 [patent_title] => 'Method of making a semiconductor device having multilayer structure' [patent_app_type] => 1 [patent_app_number] => 7/818237 [patent_app_country] => US [patent_app_date] => 1992-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 47 [patent_no_of_words] => 10792 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/229/05229313.pdf [firstpage_image] =>[orig_patent_app_number] => 818237 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/818237
Method of making a semiconductor device having multilayer structure Jan 7, 1992 Issued
Array ( [id] => 2985318 [patent_doc_number] => 05266516 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-30 [patent_title] => 'Method for making electrical contact through an opening of one micron or less for CMOS technology' [patent_app_type] => 1 [patent_app_number] => 7/815745 [patent_app_country] => US [patent_app_date] => 1992-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2618 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/266/05266516.pdf [firstpage_image] =>[orig_patent_app_number] => 815745 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/815745
Method for making electrical contact through an opening of one micron or less for CMOS technology Jan 1, 1992 Issued
Array ( [id] => 2973730 [patent_doc_number] => 05225357 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Low P+ contact resistance formation by double implant' [patent_app_type] => 1 [patent_app_number] => 7/815515 [patent_app_country] => US [patent_app_date] => 1992-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 1599 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/225/05225357.pdf [firstpage_image] =>[orig_patent_app_number] => 815515 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/815515
Low P+ contact resistance formation by double implant Jan 1, 1992 Issued
Array ( [id] => 3443943 [patent_doc_number] => 05420048 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'Manufacturing method for SOI-type thin film transistor' [patent_app_type] => 1 [patent_app_number] => 7/815021 [patent_app_country] => US [patent_app_date] => 1991-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 5045 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/420/05420048.pdf [firstpage_image] =>[orig_patent_app_number] => 815021 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/815021
Manufacturing method for SOI-type thin film transistor Dec 30, 1991 Issued
Array ( [id] => 2976175 [patent_doc_number] => 05252501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-12 [patent_title] => 'Self-aligned single-mask CMOS/BiCMOS twin-well formation with flat surface topography' [patent_app_type] => 1 [patent_app_number] => 7/814547 [patent_app_country] => US [patent_app_date] => 1991-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1633 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/252/05252501.pdf [firstpage_image] =>[orig_patent_app_number] => 814547 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/814547
Self-aligned single-mask CMOS/BiCMOS twin-well formation with flat surface topography Dec 29, 1991 Issued
Array ( [id] => 2973712 [patent_doc_number] => 05225356 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Method of making field-effect semiconductor device on SOT' [patent_app_type] => 1 [patent_app_number] => 7/815815 [patent_app_country] => US [patent_app_date] => 1991-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 4459 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/225/05225356.pdf [firstpage_image] =>[orig_patent_app_number] => 815815 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/815815
Method of making field-effect semiconductor device on SOT Dec 29, 1991 Issued
Array ( [id] => 3073590 [patent_doc_number] => 05296394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Manufacturing method of GaAs metal semiconductor FET' [patent_app_type] => 1 [patent_app_number] => 7/812615 [patent_app_country] => US [patent_app_date] => 1991-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 1556 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/296/05296394.pdf [firstpage_image] =>[orig_patent_app_number] => 812615 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/812615
Manufacturing method of GaAs metal semiconductor FET Dec 25, 1991 Issued
Array ( [id] => 2909933 [patent_doc_number] => 05236854 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-17 [patent_title] => 'Compound semiconductor device and method for fabrication thereof' [patent_app_type] => 1 [patent_app_number] => 7/813479 [patent_app_country] => US [patent_app_date] => 1991-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 5051 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/236/05236854.pdf [firstpage_image] =>[orig_patent_app_number] => 813479 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/813479
Compound semiconductor device and method for fabrication thereof Dec 25, 1991 Issued
Array ( [id] => 2829448 [patent_doc_number] => 05175117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-29 [patent_title] => 'Method for making buried isolation' [patent_app_type] => 1 [patent_app_number] => 7/812499 [patent_app_country] => US [patent_app_date] => 1991-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2432 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/175/05175117.pdf [firstpage_image] =>[orig_patent_app_number] => 812499 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/812499
Method for making buried isolation Dec 22, 1991 Issued
Array ( [id] => 2865927 [patent_doc_number] => 05162252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-10 [patent_title] => 'Method of fabricating IIL and vertical complementary bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 7/808691 [patent_app_country] => US [patent_app_date] => 1991-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 7679 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/162/05162252.pdf [firstpage_image] =>[orig_patent_app_number] => 808691 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/808691
Method of fabricating IIL and vertical complementary bipolar transistors Dec 16, 1991 Issued
Array ( [id] => 2986059 [patent_doc_number] => 05212108 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-18 [patent_title] => 'Fabrication of stabilized polysilicon resistors for SEU control' [patent_app_type] => 1 [patent_app_number] => 7/807307 [patent_app_country] => US [patent_app_date] => 1991-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1857 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/212/05212108.pdf [firstpage_image] =>[orig_patent_app_number] => 807307 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/807307
Fabrication of stabilized polysilicon resistors for SEU control Dec 12, 1991 Issued
Array ( [id] => 2930040 [patent_doc_number] => 05219773 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-15 [patent_title] => 'Method of making reoxidized nitrided oxide MOSFETs' [patent_app_type] => 1 [patent_app_number] => 7/803691 [patent_app_country] => US [patent_app_date] => 1991-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 3130 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/219/05219773.pdf [firstpage_image] =>[orig_patent_app_number] => 803691 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/803691
Method of making reoxidized nitrided oxide MOSFETs Dec 2, 1991 Issued
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