Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
07/747983 METHOD OF PRODUCING SEMICONDUCTOR DEVICE INCLUDING SCHOTTKY BARRIER DIODE Aug 20, 1991 Abandoned
Array ( [id] => 2960667 [patent_doc_number] => 05273929 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-28 [patent_title] => 'Method of manufacture transistor having gradient doping during lateral epitaxy' [patent_app_type] => 1 [patent_app_number] => 7/747013 [patent_app_country] => US [patent_app_date] => 1991-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 2371 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/273/05273929.pdf [firstpage_image] =>[orig_patent_app_number] => 747013 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/747013
Method of manufacture transistor having gradient doping during lateral epitaxy Aug 18, 1991 Issued
Array ( [id] => 2804624 [patent_doc_number] => 05147824 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-15 [patent_title] => 'Semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 7/745803 [patent_app_country] => US [patent_app_date] => 1991-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 5024 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/147/05147824.pdf [firstpage_image] =>[orig_patent_app_number] => 745803 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/745803
Semiconductor wafer Aug 15, 1991 Issued
Array ( [id] => 2930022 [patent_doc_number] => 05219772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-15 [patent_title] => 'Method for making field effect devices with ultra-short gates' [patent_app_type] => 1 [patent_app_number] => 7/745589 [patent_app_country] => US [patent_app_date] => 1991-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1903 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/219/05219772.pdf [firstpage_image] =>[orig_patent_app_number] => 745589 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/745589
Method for making field effect devices with ultra-short gates Aug 14, 1991 Issued
Array ( [id] => 2877478 [patent_doc_number] => 05185274 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-09 [patent_title] => 'Self-aligned, self-passivated advanced dual lift-off heterojunction bipolar transistor method' [patent_app_type] => 1 [patent_app_number] => 7/746259 [patent_app_country] => US [patent_app_date] => 1991-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2353 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/185/05185274.pdf [firstpage_image] =>[orig_patent_app_number] => 746259 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/746259
Self-aligned, self-passivated advanced dual lift-off heterojunction bipolar transistor method Aug 14, 1991 Issued
07/721873 SEMICONDUCTOR DEVICE HAVING DIFFERENT IMPURITY CONCENTRATION WELLS Aug 7, 1991 Abandoned
07/740419 SEMICONDUCTOR DEVICE FABRICATION PROCESS Aug 4, 1991 Abandoned
07/737733 CHANNEL STOP STRUCTURE FOR CMOS DEVICES Jul 30, 1991 Abandoned
Array ( [id] => 2787105 [patent_doc_number] => 05100810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-31 [patent_title] => 'Manufacturing method of semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 7/738443 [patent_app_country] => US [patent_app_date] => 1991-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 5655 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 364 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/100/05100810.pdf [firstpage_image] =>[orig_patent_app_number] => 738443 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/738443
Manufacturing method of semiconductor devices Jul 30, 1991 Issued
Array ( [id] => 2772341 [patent_doc_number] => 05132236 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-21 [patent_title] => 'Method of semiconductor manufacture using an inverse self-aligned mask' [patent_app_type] => 1 [patent_app_number] => 7/738175 [patent_app_country] => US [patent_app_date] => 1991-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 2553 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/132/05132236.pdf [firstpage_image] =>[orig_patent_app_number] => 738175 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/738175
Method of semiconductor manufacture using an inverse self-aligned mask Jul 29, 1991 Issued
07/738029 GIGAOHM LOAD RESISTOR FOR BICOMS PROCESS Jul 29, 1991 Abandoned
07/736743 DEVICE AND METHOD FOR PRODUCING A FULLY WALLED EMITTER-BASE STRUCTURE IN A BIPOLAR TRANSISTOR Jul 25, 1991 Abandoned
Array ( [id] => 2871117 [patent_doc_number] => 05091321 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-25 [patent_title] => 'Method for making an NPN transistor with controlled base width compatible with making a Bi-MOS integrated circuit' [patent_app_type] => 1 [patent_app_number] => 7/733919 [patent_app_country] => US [patent_app_date] => 1991-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1899 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/091/05091321.pdf [firstpage_image] =>[orig_patent_app_number] => 733919 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/733919
Method for making an NPN transistor with controlled base width compatible with making a Bi-MOS integrated circuit Jul 21, 1991 Issued
Array ( [id] => 2894548 [patent_doc_number] => 05183768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-02 [patent_title] => 'Method of fabricating semiconductor device by forming doped regions that limit width of the base' [patent_app_type] => 1 [patent_app_number] => 7/729965 [patent_app_country] => US [patent_app_date] => 1991-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 6625 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/183/05183768.pdf [firstpage_image] =>[orig_patent_app_number] => 729965 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/729965
Method of fabricating semiconductor device by forming doped regions that limit width of the base Jul 14, 1991 Issued
Array ( [id] => 2966672 [patent_doc_number] => 05202273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-13 [patent_title] => 'Method of manufacturing a vertical semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/729239 [patent_app_country] => US [patent_app_date] => 1991-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 5460 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 365 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/202/05202273.pdf [firstpage_image] =>[orig_patent_app_number] => 729239 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/729239
Method of manufacturing a vertical semiconductor device Jul 11, 1991 Issued
07/726730 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING ELEMENTS ISOLATED BY TRENCH Jul 1, 1991 Abandoned
Array ( [id] => 2890115 [patent_doc_number] => 05270223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-14 [patent_title] => 'Multiple layer wide bandgap collector structure for bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 7/723111 [patent_app_country] => US [patent_app_date] => 1991-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4689 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/270/05270223.pdf [firstpage_image] =>[orig_patent_app_number] => 723111 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/723111
Multiple layer wide bandgap collector structure for bipolar transistors Jun 27, 1991 Issued
Array ( [id] => 2854774 [patent_doc_number] => 05166088 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-24 [patent_title] => 'Method of manufacturing semiconductor device contact vias in layers comprising silicon nitride and glass' [patent_app_type] => 1 [patent_app_number] => 7/719737 [patent_app_country] => US [patent_app_date] => 1991-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4325 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/166/05166088.pdf [firstpage_image] =>[orig_patent_app_number] => 719737 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/719737
Method of manufacturing semiconductor device contact vias in layers comprising silicon nitride and glass Jun 24, 1991 Issued
Array ( [id] => 2845802 [patent_doc_number] => 05110749 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-05 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/714723 [patent_app_country] => US [patent_app_date] => 1991-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 28 [patent_no_of_words] => 4336 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/110/05110749.pdf [firstpage_image] =>[orig_patent_app_number] => 714723 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/714723
Method for manufacturing semiconductor device Jun 12, 1991 Issued
Array ( [id] => 2854664 [patent_doc_number] => 05166082 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-24 [patent_title] => 'BIMOS transistor devices having bipolar and MOS transistors formed in substrate thereof and process for the fabrication of the same' [patent_app_type] => 1 [patent_app_number] => 7/712713 [patent_app_country] => US [patent_app_date] => 1991-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 35 [patent_no_of_words] => 5445 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/166/05166082.pdf [firstpage_image] =>[orig_patent_app_number] => 712713 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/712713
BIMOS transistor devices having bipolar and MOS transistors formed in substrate thereof and process for the fabrication of the same Jun 9, 1991 Issued
Menu