Long Pham

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Array ( [id] => 2822948 [patent_doc_number] => 05169793 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-08 [patent_title] => 'Method of making an insulated gate bipolar transistor having gate shield region' [patent_app_type] => 1 [patent_app_number] => 7/710721 [patent_app_country] => US [patent_app_date] => 1991-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 5760 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 550 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/169/05169793.pdf [firstpage_image] =>[orig_patent_app_number] => 710721 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 3093648 [patent_doc_number] => 05298441 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-29 [patent_title] => 'Method of making high transconductance heterostructure field effect transistor' [patent_app_type] => 1 [patent_app_number] => 7/709741 [patent_app_country] => US [patent_app_date] => 1991-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3488 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/298/05298441.pdf [firstpage_image] =>[orig_patent_app_number] => 709741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2840171 [patent_doc_number] => 05137839 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-11 [patent_title] => 'Method of manufacturing a bipolar transistor having polysilicon layer which serves as an emitter electrode and passivating dangling bonds' [patent_app_type] => 1 [patent_app_number] => 7/705497 [patent_app_country] => US [patent_app_date] => 1991-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1848 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/137/05137839.pdf [firstpage_image] =>[orig_patent_app_number] => 705497 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 2894569 [patent_doc_number] => 05183769 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-02 [patent_title] => 'Vertical current flow semiconductor device utilizing wafer bonding' [patent_app_type] => 1 [patent_app_number] => 7/696405 [patent_app_country] => US [patent_app_date] => 1991-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2141 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/183/05183769.pdf [firstpage_image] =>[orig_patent_app_number] => 696405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2874945 [patent_doc_number] => 05158899 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-27 [patent_title] => 'Method of manufacturing input circuit of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/696419 [patent_app_country] => US [patent_app_date] => 1991-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 4849 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/158/05158899.pdf [firstpage_image] =>[orig_patent_app_number] => 696419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2734565 [patent_doc_number] => 05077226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-31 [patent_title] => 'Manufacturing method for BiCMOS devices' [patent_app_type] => 1 [patent_app_number] => 7/692713 [patent_app_country] => US [patent_app_date] => 1991-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2857 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 438 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/077/05077226.pdf [firstpage_image] =>[orig_patent_app_number] => 692713 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2891305 [patent_doc_number] => 05177026 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-05 [patent_title] => 'Method for producing a compound semiconductor MIS FET' [patent_app_type] => 1 [patent_app_number] => 7/686831 [patent_app_country] => US [patent_app_date] => 1991-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 1981 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/177/05177026.pdf [firstpage_image] =>[orig_patent_app_number] => 686831 [rel_patent_id] =>[rel_patent_doc_number] =>)

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