| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_issue_date] => 1991-12-17
[patent_title] => 'Method for making a self-aligned lateral bipolar SOI transistor'
[patent_app_type] => 1
[patent_app_number] => 7/655477
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[patent_app_date] => 1991-02-14
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[firstpage_image] =>[orig_patent_app_number] => 655477
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Array
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[patent_doc_number] => 05213988
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[patent_kind] => NA
[patent_issue_date] => 1993-05-25
[patent_title] => 'Method of manufacturing bipolar transistor with self-aligned base regions'
[patent_app_type] => 1
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[patent_app_date] => 1991-02-07
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[firstpage_image] =>[orig_patent_app_number] => 652785
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/652785 | Method of manufacturing bipolar transistor with self-aligned base regions | Feb 6, 1991 | Issued |
Array
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[patent_doc_number] => 05385850
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-31
[patent_title] => 'Method of forming a doped region in a semiconductor substrate utilizing a sacrificial epitaxial silicon layer'
[patent_app_type] => 1
[patent_app_number] => 7/652339
[patent_app_country] => US
[patent_app_date] => 1991-02-07
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/652339 | Method of forming a doped region in a semiconductor substrate utilizing a sacrificial epitaxial silicon layer | Feb 6, 1991 | Issued |
Array
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[id] => 2782701
[patent_doc_number] => 05154946
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-13
[patent_title] => 'CMOS structure fabrication'
[patent_app_type] => 1
[patent_app_number] => 7/649189
[patent_app_country] => US
[patent_app_date] => 1991-02-04
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 649189
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/649189 | CMOS structure fabrication | Feb 3, 1991 | Issued |
| 07/648973 | INSULATED GATE BIPOLAR TRANSISTOR AND METHOD OF FABRICATING THE SAME | Jan 30, 1991 | Abandoned |
Array
(
[id] => 2851242
[patent_doc_number] => 05089433
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-02-18
[patent_title] => 'Bipolar field-effect electrically erasable programmable read only memory cell and method of manufacture'
[patent_app_type] => 1
[patent_app_number] => 7/647185
[patent_app_country] => US
[patent_app_date] => 1991-01-24
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[firstpage_image] =>[orig_patent_app_number] => 647185
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/647185 | Bipolar field-effect electrically erasable programmable read only memory cell and method of manufacture | Jan 23, 1991 | Issued |
| 07/643907 | HIGH PERFORMANCE/HIGH DENSITY BICMOS PROCESS | Jan 17, 1991 | Abandoned |
Array
(
[id] => 2787122
[patent_doc_number] => 05100811
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[patent_kind] => NA
[patent_issue_date] => 1992-03-31
[patent_title] => 'Integrated circuit containing bi-polar and complementary MOS transistors on a common substrate and method for the manufacture thereof'
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[firstpage_image] =>[orig_patent_app_number] => 632411
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/632411 | Integrated circuit containing bi-polar and complementary MOS transistors on a common substrate and method for the manufacture thereof | Dec 20, 1990 | Issued |
Array
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[id] => 2787177
[patent_doc_number] => 05100814
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-03-31
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 7/628007
[patent_app_country] => US
[patent_app_date] => 1990-12-17
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[pdf_file] => patents/05/100/05100814.pdf
[firstpage_image] =>[orig_patent_app_number] => 628007
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/628007 | Semiconductor device and method of manufacturing the same | Dec 16, 1990 | Issued |
Array
(
[id] => 2920928
[patent_doc_number] => 05192699
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-09
[patent_title] => 'Method of fabricating field effect transistors'
[patent_app_type] => 1
[patent_app_number] => 7/628763
[patent_app_country] => US
[patent_app_date] => 1990-12-17
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[firstpage_image] =>[orig_patent_app_number] => 628763
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/628763 | Method of fabricating field effect transistors | Dec 16, 1990 | Issued |
Array
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[id] => 2668326
[patent_doc_number] => 05070031
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[patent_kind] => NA
[patent_issue_date] => 1991-12-03
[patent_title] => 'Complementary semiconductor region fabrication'
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[firstpage_image] =>[orig_patent_app_number] => 627477
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/627477 | Complementary semiconductor region fabrication | Dec 13, 1990 | Issued |
Array
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[id] => 2958064
[patent_doc_number] => 05198378
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-30
[patent_title] => 'Process of fabricating elevated source/drain transistor'
[patent_app_type] => 1
[patent_app_number] => 7/609969
[patent_app_country] => US
[patent_app_date] => 1990-12-10
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[firstpage_image] =>[orig_patent_app_number] => 609969
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/609969 | Process of fabricating elevated source/drain transistor | Dec 9, 1990 | Issued |
Array
(
[id] => 2784515
[patent_doc_number] => 05093272
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-03-03
[patent_title] => 'Manufacturing method for a self-aligned emitter-base-complex for heterobipolar transistors'
[patent_app_type] => 1
[patent_app_number] => 7/620625
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[firstpage_image] =>[orig_patent_app_number] => 620625
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/620625 | Manufacturing method for a self-aligned emitter-base-complex for heterobipolar transistors | Dec 2, 1990 | Issued |
Array
(
[id] => 2850638
[patent_doc_number] => 05126278
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-06-30
[patent_title] => 'Method of manufacturing bipolar transistor by implanting intrinsic impurities'
[patent_app_type] => 1
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[patent_app_country] => US
[patent_app_date] => 1990-11-19
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[firstpage_image] =>[orig_patent_app_number] => 615235
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/615235 | Method of manufacturing bipolar transistor by implanting intrinsic impurities | Nov 18, 1990 | Issued |
| 07/613191 | BICMOS PROCESS WITH LOW BASE RECOMBINATION CURRENT BIPOLAR TRANSISTORS | Nov 13, 1990 | Abandoned |
Array
(
[id] => 2875682
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[firstpage_image] =>[orig_patent_app_number] => 609801
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/609801 | Dual layer surface gate JFET having enhanced gate-channel breakdown voltage | Nov 4, 1990 | Issued |
Array
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[patent_issue_date] => 1994-04-26
[patent_title] => 'Method of making silicon MESFET for dielectrically isolated integrated circuits'
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[patent_app_number] => 7/606193
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/606193 | Method of making silicon MESFET for dielectrically isolated integrated circuits | Oct 30, 1990 | Issued |
Array
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[firstpage_image] =>[orig_patent_app_number] => 605623
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/605623 | Insulator assisted self-aligned gate junction | Oct 29, 1990 | Issued |
Array
(
[id] => 2844878
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[patent_issue_date] => 1992-04-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/571457 | Compound semiconductor device and a manufacturing method thereof | Oct 24, 1990 | Issued |