Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2671451 [patent_doc_number] => 05073506 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-17 [patent_title] => 'Method for making a self-aligned lateral bipolar SOI transistor' [patent_app_type] => 1 [patent_app_number] => 7/655477 [patent_app_country] => US [patent_app_date] => 1991-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 8 [patent_no_of_words] => 2224 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/073/05073506.pdf [firstpage_image] =>[orig_patent_app_number] => 655477 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/655477
Method for making a self-aligned lateral bipolar SOI transistor Feb 13, 1991 Issued
Array ( [id] => 2884825 [patent_doc_number] => 05213988 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-25 [patent_title] => 'Method of manufacturing bipolar transistor with self-aligned base regions' [patent_app_type] => 1 [patent_app_number] => 7/652785 [patent_app_country] => US [patent_app_date] => 1991-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 2597 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/213/05213988.pdf [firstpage_image] =>[orig_patent_app_number] => 652785 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/652785
Method of manufacturing bipolar transistor with self-aligned base regions Feb 6, 1991 Issued
Array ( [id] => 3450152 [patent_doc_number] => 05385850 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-31 [patent_title] => 'Method of forming a doped region in a semiconductor substrate utilizing a sacrificial epitaxial silicon layer' [patent_app_type] => 1 [patent_app_number] => 7/652339 [patent_app_country] => US [patent_app_date] => 1991-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3276 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/385/05385850.pdf [firstpage_image] =>[orig_patent_app_number] => 652339 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/652339
Method of forming a doped region in a semiconductor substrate utilizing a sacrificial epitaxial silicon layer Feb 6, 1991 Issued
Array ( [id] => 2782701 [patent_doc_number] => 05154946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-13 [patent_title] => 'CMOS structure fabrication' [patent_app_type] => 1 [patent_app_number] => 7/649189 [patent_app_country] => US [patent_app_date] => 1991-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2580 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/154/05154946.pdf [firstpage_image] =>[orig_patent_app_number] => 649189 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/649189
CMOS structure fabrication Feb 3, 1991 Issued
07/648973 INSULATED GATE BIPOLAR TRANSISTOR AND METHOD OF FABRICATING THE SAME Jan 30, 1991 Abandoned
Array ( [id] => 2851242 [patent_doc_number] => 05089433 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-18 [patent_title] => 'Bipolar field-effect electrically erasable programmable read only memory cell and method of manufacture' [patent_app_type] => 1 [patent_app_number] => 7/647185 [patent_app_country] => US [patent_app_date] => 1991-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 3343 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/089/05089433.pdf [firstpage_image] =>[orig_patent_app_number] => 647185 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/647185
Bipolar field-effect electrically erasable programmable read only memory cell and method of manufacture Jan 23, 1991 Issued
07/643907 HIGH PERFORMANCE/HIGH DENSITY BICMOS PROCESS Jan 17, 1991 Abandoned
Array ( [id] => 2787122 [patent_doc_number] => 05100811 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-31 [patent_title] => 'Integrated circuit containing bi-polar and complementary MOS transistors on a common substrate and method for the manufacture thereof' [patent_app_type] => 1 [patent_app_number] => 7/632411 [patent_app_country] => US [patent_app_date] => 1990-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 3257 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/100/05100811.pdf [firstpage_image] =>[orig_patent_app_number] => 632411 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/632411
Integrated circuit containing bi-polar and complementary MOS transistors on a common substrate and method for the manufacture thereof Dec 20, 1990 Issued
Array ( [id] => 2787177 [patent_doc_number] => 05100814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-31 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 7/628007 [patent_app_country] => US [patent_app_date] => 1990-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 3600 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/100/05100814.pdf [firstpage_image] =>[orig_patent_app_number] => 628007 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/628007
Semiconductor device and method of manufacturing the same Dec 16, 1990 Issued
Array ( [id] => 2920928 [patent_doc_number] => 05192699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-09 [patent_title] => 'Method of fabricating field effect transistors' [patent_app_type] => 1 [patent_app_number] => 7/628763 [patent_app_country] => US [patent_app_date] => 1990-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 2650 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/192/05192699.pdf [firstpage_image] =>[orig_patent_app_number] => 628763 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/628763
Method of fabricating field effect transistors Dec 16, 1990 Issued
Array ( [id] => 2668326 [patent_doc_number] => 05070031 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-03 [patent_title] => 'Complementary semiconductor region fabrication' [patent_app_type] => 1 [patent_app_number] => 7/627477 [patent_app_country] => US [patent_app_date] => 1990-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1868 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/070/05070031.pdf [firstpage_image] =>[orig_patent_app_number] => 627477 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/627477
Complementary semiconductor region fabrication Dec 13, 1990 Issued
Array ( [id] => 2958064 [patent_doc_number] => 05198378 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-30 [patent_title] => 'Process of fabricating elevated source/drain transistor' [patent_app_type] => 1 [patent_app_number] => 7/609969 [patent_app_country] => US [patent_app_date] => 1990-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 8 [patent_no_of_words] => 3039 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/198/05198378.pdf [firstpage_image] =>[orig_patent_app_number] => 609969 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/609969
Process of fabricating elevated source/drain transistor Dec 9, 1990 Issued
Array ( [id] => 2784515 [patent_doc_number] => 05093272 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-03 [patent_title] => 'Manufacturing method for a self-aligned emitter-base-complex for heterobipolar transistors' [patent_app_type] => 1 [patent_app_number] => 7/620625 [patent_app_country] => US [patent_app_date] => 1990-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 12 [patent_no_of_words] => 2349 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/093/05093272.pdf [firstpage_image] =>[orig_patent_app_number] => 620625 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/620625
Manufacturing method for a self-aligned emitter-base-complex for heterobipolar transistors Dec 2, 1990 Issued
Array ( [id] => 2850638 [patent_doc_number] => 05126278 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-30 [patent_title] => 'Method of manufacturing bipolar transistor by implanting intrinsic impurities' [patent_app_type] => 1 [patent_app_number] => 7/615235 [patent_app_country] => US [patent_app_date] => 1990-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2369 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/126/05126278.pdf [firstpage_image] =>[orig_patent_app_number] => 615235 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/615235
Method of manufacturing bipolar transistor by implanting intrinsic impurities Nov 18, 1990 Issued
07/613191 BICMOS PROCESS WITH LOW BASE RECOMBINATION CURRENT BIPOLAR TRANSISTORS Nov 13, 1990 Abandoned
Array ( [id] => 2875682 [patent_doc_number] => 05118632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-02 [patent_title] => 'Dual layer surface gate JFET having enhanced gate-channel breakdown voltage' [patent_app_type] => 1 [patent_app_number] => 7/609801 [patent_app_country] => US [patent_app_date] => 1990-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3373 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/118/05118632.pdf [firstpage_image] =>[orig_patent_app_number] => 609801 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/609801
Dual layer surface gate JFET having enhanced gate-channel breakdown voltage Nov 4, 1990 Issued
Array ( [id] => 3049498 [patent_doc_number] => 05306650 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-26 [patent_title] => 'Method of making silicon MESFET for dielectrically isolated integrated circuits' [patent_app_type] => 1 [patent_app_number] => 7/606193 [patent_app_country] => US [patent_app_date] => 1990-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1668 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/306/05306650.pdf [firstpage_image] =>[orig_patent_app_number] => 606193 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/606193
Method of making silicon MESFET for dielectrically isolated integrated circuits Oct 30, 1990 Issued
Array ( [id] => 2743130 [patent_doc_number] => 05011785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-30 [patent_title] => 'Insulator assisted self-aligned gate junction' [patent_app_type] => 1 [patent_app_number] => 7/605623 [patent_app_country] => US [patent_app_date] => 1990-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 1964 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/011/05011785.pdf [firstpage_image] =>[orig_patent_app_number] => 605623 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/605623
Insulator assisted self-aligned gate junction Oct 29, 1990 Issued
Array ( [id] => 2844878 [patent_doc_number] => 05106766 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-21 [patent_title] => 'Method of making a semiconductor device that comprises p-type III-V semiconductor material' [patent_app_type] => 1 [patent_app_number] => 7/606003 [patent_app_country] => US [patent_app_date] => 1990-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3323 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/106/05106766.pdf [firstpage_image] =>[orig_patent_app_number] => 606003 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/606003
Method of making a semiconductor device that comprises p-type III-V semiconductor material Oct 29, 1990 Issued
Array ( [id] => 2722615 [patent_doc_number] => 05024958 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-18 [patent_title] => 'Compound semiconductor device and a manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 7/571457 [patent_app_country] => US [patent_app_date] => 1990-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 5607 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/024/05024958.pdf [firstpage_image] =>[orig_patent_app_number] => 571457 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/571457
Compound semiconductor device and a manufacturing method thereof Oct 24, 1990 Issued
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