Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2887595 [patent_doc_number] => 05238876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-24 [patent_title] => 'Method of dividing semiconductor wafer using ultraviolet sensitive tape' [patent_app_type] => 1 [patent_app_number] => 7/554436 [patent_app_country] => US [patent_app_date] => 1990-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3317 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/238/05238876.pdf [firstpage_image] =>[orig_patent_app_number] => 554436 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/554436
Method of dividing semiconductor wafer using ultraviolet sensitive tape Jul 18, 1990 Issued
Array ( [id] => 2754412 [patent_doc_number] => 05043301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-27 [patent_title] => 'Method of thermally treating semiconductor wafers in furnace and wafer hanger useful therein' [patent_app_type] => 1 [patent_app_number] => 7/554387 [patent_app_country] => US [patent_app_date] => 1990-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 27 [patent_no_of_words] => 6435 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/043/05043301.pdf [firstpage_image] =>[orig_patent_app_number] => 554387 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/554387
Method of thermally treating semiconductor wafers in furnace and wafer hanger useful therein Jul 18, 1990 Issued
07/554448 OXIDATION METHOD Jul 18, 1990 Abandoned
Array ( [id] => 2722673 [patent_doc_number] => 05024961 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-18 [patent_title] => 'Blanket punchthrough and field-isolation implant for sub-micron N-channel CMOS devices' [patent_app_type] => 1 [patent_app_number] => 7/550000 [patent_app_country] => US [patent_app_date] => 1990-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1726 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/024/05024961.pdf [firstpage_image] =>[orig_patent_app_number] => 550000 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/550000
Blanket punchthrough and field-isolation implant for sub-micron N-channel CMOS devices Jul 8, 1990 Issued
Array ( [id] => 2668891 [patent_doc_number] => 05034342 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-23 [patent_title] => 'Method of forming semiconductor stalk structure by epitaxial growth in trench' [patent_app_type] => 1 [patent_app_number] => 7/546289 [patent_app_country] => US [patent_app_date] => 1990-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 2247 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/034/05034342.pdf [firstpage_image] =>[orig_patent_app_number] => 546289 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/546289
Method of forming semiconductor stalk structure by epitaxial growth in trench Jun 28, 1990 Issued
Array ( [id] => 2750728 [patent_doc_number] => 05071778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-10 [patent_title] => 'Self-aligned collector implant for bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 7/543907 [patent_app_country] => US [patent_app_date] => 1990-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 24 [patent_no_of_words] => 6114 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/071/05071778.pdf [firstpage_image] =>[orig_patent_app_number] => 543907 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/543907
Self-aligned collector implant for bipolar transistors Jun 25, 1990 Issued
Array ( [id] => 2802338 [patent_doc_number] => 05145795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-08 [patent_title] => 'Semiconductor device and method therefore' [patent_app_type] => 1 [patent_app_number] => 7/543233 [patent_app_country] => US [patent_app_date] => 1990-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 4222 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/145/05145795.pdf [firstpage_image] =>[orig_patent_app_number] => 543233 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/543233
Semiconductor device and method therefore Jun 24, 1990 Issued
Array ( [id] => 2822891 [patent_doc_number] => 05094973 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-10 [patent_title] => 'Trench pillar for wafer processing' [patent_app_type] => 1 [patent_app_number] => 7/541676 [patent_app_country] => US [patent_app_date] => 1990-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1376 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/094/05094973.pdf [firstpage_image] =>[orig_patent_app_number] => 541676 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/541676
Trench pillar for wafer processing Jun 20, 1990 Issued
Array ( [id] => 2732730 [patent_doc_number] => 05032528 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-16 [patent_title] => 'Method of forming a contact hole in semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 7/538764 [patent_app_country] => US [patent_app_date] => 1990-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 14 [patent_no_of_words] => 2823 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/032/05032528.pdf [firstpage_image] =>[orig_patent_app_number] => 538764 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/538764
Method of forming a contact hole in semiconductor integrated circuit Jun 14, 1990 Issued
07/534479 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING ELEMENTS ISOLATED BY TRENCH Jun 6, 1990 Abandoned
Array ( [id] => 2754267 [patent_doc_number] => 05043293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-27 [patent_title] => 'Dual oxide channel stop for semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 7/532153 [patent_app_country] => US [patent_app_date] => 1990-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2394 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/043/05043293.pdf [firstpage_image] =>[orig_patent_app_number] => 532153 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/532153
Dual oxide channel stop for semiconductor devices May 31, 1990 Issued
Array ( [id] => 2681514 [patent_doc_number] => 05045493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-03 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 7/514167 [patent_app_country] => US [patent_app_date] => 1990-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 34 [patent_no_of_words] => 10049 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/045/05045493.pdf [firstpage_image] =>[orig_patent_app_number] => 514167 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/514167
Semiconductor device and method of manufacturing the same Apr 23, 1990 Issued
Array ( [id] => 2686309 [patent_doc_number] => 05016332 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-21 [patent_title] => 'Plasma reactor and process with wafer temperature control' [patent_app_type] => 1 [patent_app_number] => 7/509379 [patent_app_country] => US [patent_app_date] => 1990-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1632 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/016/05016332.pdf [firstpage_image] =>[orig_patent_app_number] => 509379 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/509379
Plasma reactor and process with wafer temperature control Apr 12, 1990 Issued
Array ( [id] => 2812839 [patent_doc_number] => 05079182 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-07 [patent_title] => 'BiCMOS device having self-aligned well tap and method of fabrication' [patent_app_type] => 1 [patent_app_number] => 7/503345 [patent_app_country] => US [patent_app_date] => 1990-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 5422 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/079/05079182.pdf [firstpage_image] =>[orig_patent_app_number] => 503345 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/503345
BiCMOS device having self-aligned well tap and method of fabrication Apr 1, 1990 Issued
Array ( [id] => 2783274 [patent_doc_number] => 05141878 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-25 [patent_title] => 'Silicon photodiode for monolithic integrated circuits and method for making same' [patent_app_type] => 1 [patent_app_number] => 7/503193 [patent_app_country] => US [patent_app_date] => 1990-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2360 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/141/05141878.pdf [firstpage_image] =>[orig_patent_app_number] => 503193 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/503193
Silicon photodiode for monolithic integrated circuits and method for making same Apr 1, 1990 Issued
07/503419 TRANSISTOR DEVICE WITH INCREASED BREAKDOWN VOLTAGE AND METHOD OF FABRICATION Apr 1, 1990 Abandoned
Array ( [id] => 2667976 [patent_doc_number] => 05047356 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-10 [patent_title] => 'High speed silicon-on-insulator device and process of fabricating same' [patent_app_type] => 1 [patent_app_number] => 7/481032 [patent_app_country] => US [patent_app_date] => 1990-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 14 [patent_no_of_words] => 2495 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/047/05047356.pdf [firstpage_image] =>[orig_patent_app_number] => 481032 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/481032
High speed silicon-on-insulator device and process of fabricating same Feb 15, 1990 Issued
Array ( [id] => 2771557 [patent_doc_number] => 05075242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-24 [patent_title] => 'Method of manufacturing CMOS semiconductor device having decreased diffusion layer capacitance' [patent_app_type] => 1 [patent_app_number] => 7/450570 [patent_app_country] => US [patent_app_date] => 1989-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3402 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/075/05075242.pdf [firstpage_image] =>[orig_patent_app_number] => 450570 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/450570
Method of manufacturing CMOS semiconductor device having decreased diffusion layer capacitance Dec 13, 1989 Issued
07/446981 SEMICONDUCTOR DEVICE Dec 5, 1989 Abandoned
Array ( [id] => 2789386 [patent_doc_number] => 05102812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-07 [patent_title] => 'Method of making a lateral bipolar heterojunction structure' [patent_app_type] => 1 [patent_app_number] => 7/433847 [patent_app_country] => US [patent_app_date] => 1989-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2928 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/102/05102812.pdf [firstpage_image] =>[orig_patent_app_number] => 433847 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/433847
Method of making a lateral bipolar heterojunction structure Nov 8, 1989 Issued
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