Search

Long Pham

Examiner (ID: 2012, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2823, 1107, 2822, 2812, 2814, 2897, 1763, 2899
Total Applications
3736
Issued Applications
3294
Pending Applications
136
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20540171 [patent_doc_number] => 12557258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/601094 [patent_app_country] => US [patent_app_date] => 2024-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 36 [patent_no_of_words] => 3201 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601094 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/601094
Semiconductor device and manufacturing method thereof Mar 10, 2024 Issued
Array ( [id] => 19269509 [patent_doc_number] => 20240213213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => EMBEDDED STRESS ABSORBER IN PACKAGE [patent_app_type] => utility [patent_app_number] => 18/599734 [patent_app_country] => US [patent_app_date] => 2024-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18599734 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/599734
Embedded stress absorber in package Mar 7, 2024 Issued
Array ( [id] => 20496914 [patent_doc_number] => 12538808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Die and package structure [patent_app_type] => utility [patent_app_number] => 18/595421 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 3415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18595421 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/595421
Die and package structure Mar 4, 2024 Issued
Array ( [id] => 19560144 [patent_doc_number] => 20240371936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS [patent_app_type] => utility [patent_app_number] => 18/592519 [patent_app_country] => US [patent_app_date] => 2024-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18592519 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/592519
SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS Feb 29, 2024 Pending
Array ( [id] => 20416864 [patent_doc_number] => 12500158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Semiconductor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/587998 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 55 [patent_no_of_words] => 6377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587998 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587998
Semiconductor structure and manufacturing method thereof Feb 26, 2024 Issued
Array ( [id] => 19237543 [patent_doc_number] => 20240194738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/587981 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3309 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587981 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587981
Semiconductor device and method for fabricating the same Feb 26, 2024 Issued
Array ( [id] => 20626140 [patent_doc_number] => 12593670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Contact formation method and related structure [patent_app_type] => utility [patent_app_number] => 18/581162 [patent_app_country] => US [patent_app_date] => 2024-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 5947 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581162 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581162
Contact formation method and related structure Feb 18, 2024 Issued
Array ( [id] => 19407373 [patent_doc_number] => 20240290884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => STRESS INCORPORATION IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/441824 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7932 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18441824 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/441824
STRESS INCORPORATION IN SEMICONDUCTOR DEVICES Feb 13, 2024 Pending
Array ( [id] => 19218322 [patent_doc_number] => 20240183026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => Cooling Device and Process for Cooling Double-Sided SiP Devices During Sputtering [patent_app_type] => utility [patent_app_number] => 18/440068 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3484 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440068 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440068
Cooling device and process for cooling double-sided SiP devices during sputtering Feb 12, 2024 Issued
Array ( [id] => 20471018 [patent_doc_number] => 12527064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Power reduction in finFET structures [patent_app_type] => utility [patent_app_number] => 18/439132 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 3453 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18439132 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/439132
Power reduction in finFET structures Feb 11, 2024 Issued
Array ( [id] => 19575630 [patent_doc_number] => 20240379922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => LIGHT-EMITTING ELEMENT PACKAGE, DISPLAY DEVICE USING THE SAME, AND METHOD FOR MANUFACTURING DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/439531 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9882 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18439531 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/439531
LIGHT-EMITTING ELEMENT PACKAGE, DISPLAY DEVICE USING THE SAME, AND METHOD FOR MANUFACTURING DISPLAY DEVICE Feb 11, 2024 Pending
Array ( [id] => 19470727 [patent_doc_number] => 20240324397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/438698 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438698 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/438698
DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME Feb 11, 2024 Pending
Array ( [id] => 19335615 [patent_doc_number] => 20240250045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => METHODS RELATED TO DUAL-SIDED MODULE WITH LAND-GRID ARRAY (LGA) FOOTPRINT [patent_app_type] => utility [patent_app_number] => 18/433228 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6209 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18433228 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/433228
Methods related to dual-sided module with land-grid array (LGA) footprint Feb 4, 2024 Issued
Array ( [id] => 19176220 [patent_doc_number] => 20240162194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/421198 [patent_app_country] => US [patent_app_date] => 2024-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18421198 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/421198
Semiconductor package and method of fabricating the same Jan 23, 2024 Issued
Array ( [id] => 19351287 [patent_doc_number] => 20240260251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => Memory Circuitry And Methods Used In Forming Memory Circuitry [patent_app_type] => utility [patent_app_number] => 18/419808 [patent_app_country] => US [patent_app_date] => 2024-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18419808 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/419808
Memory Circuitry And Methods Used In Forming Memory Circuitry Jan 22, 2024 Pending
Array ( [id] => 19866425 [patent_doc_number] => 20250105211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING SIDE INTERCONNECTION [patent_app_type] => utility [patent_app_number] => 18/419558 [patent_app_country] => US [patent_app_date] => 2024-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6427 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18419558 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/419558
SEMICONDUCTOR DEVICE INCLUDING SIDE INTERCONNECTION Jan 22, 2024 Pending
Array ( [id] => 20068377 [patent_doc_number] => 20250206599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/419447 [patent_app_country] => US [patent_app_date] => 2024-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18419447 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/419447
ELECTRONIC DEVICE Jan 21, 2024 Pending
Array ( [id] => 19252990 [patent_doc_number] => 20240203987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => SEMICONDUCTOR DEVICE HAVING EPITAXY SOURCE/DRAIN REGIONS [patent_app_type] => utility [patent_app_number] => 18/415143 [patent_app_country] => US [patent_app_date] => 2024-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415143 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415143
Semiconductor device having epitaxy source/drain regions Jan 16, 2024 Issued
Array ( [id] => 19679384 [patent_doc_number] => 12191257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Electrical bridge package with integrated off-bridge photonic channel interface [patent_app_type] => utility [patent_app_number] => 18/407410 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17237 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18407410 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/407410
Electrical bridge package with integrated off-bridge photonic channel interface Jan 7, 2024 Issued
Array ( [id] => 19161180 [patent_doc_number] => 20240153887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/403974 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5050 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403974 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403974
Semiconductor package structure Jan 3, 2024 Issued
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