
Long Pham
Examiner (ID: 16756, Phone: (571)272-1714 , Office: P/2814 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2899, 2897, 1107, 2814, 1763, 2812, 2822, 2823 |
| Total Applications | 3709 |
| Issued Applications | 3257 |
| Pending Applications | 178 |
| Abandoned Applications | 335 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17414453
[patent_doc_number] => 20220049357
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-17
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
[patent_app_type] => utility
[patent_app_number] => 17/431262
[patent_app_country] => US
[patent_app_date] => 2020-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12713
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17431262
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/431262 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME | Mar 11, 2020 | Abandoned |
Array
(
[id] => 17941772
[patent_doc_number] => 11476232
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-18
[patent_title] => Three-dimensional packaging techniques for power FET density improvement
[patent_app_type] => utility
[patent_app_number] => 16/817203
[patent_app_country] => US
[patent_app_date] => 2020-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 50
[patent_no_of_words] => 7436
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16817203
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/817203 | Three-dimensional packaging techniques for power FET density improvement | Mar 11, 2020 | Issued |
Array
(
[id] => 17100234
[patent_doc_number] => 20210288025
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-16
[patent_title] => HIGH BANDWIDTH MODULE
[patent_app_type] => utility
[patent_app_number] => 16/814139
[patent_app_country] => US
[patent_app_date] => 2020-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6404
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16814139
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/814139 | High bandwidth module | Mar 9, 2020 | Issued |
Array
(
[id] => 16119843
[patent_doc_number] => 20200211944
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-02
[patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 16/813898
[patent_app_country] => US
[patent_app_date] => 2020-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8382
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16813898
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/813898 | Semiconductor package structure | Mar 9, 2020 | Issued |
Array
(
[id] => 17700430
[patent_doc_number] => 11374165
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-06-28
[patent_title] => Method of forming ultra-smooth bottom electrode surface for depositing magnetic tunnel junctions
[patent_app_type] => utility
[patent_app_number] => 16/810697
[patent_app_country] => US
[patent_app_date] => 2020-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2448
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16810697
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/810697 | Method of forming ultra-smooth bottom electrode surface for depositing magnetic tunnel junctions | Mar 4, 2020 | Issued |
Array
(
[id] => 17941781
[patent_doc_number] => 11476241
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-18
[patent_title] => Interposer, microelectronic device assembly including same and methods of fabrication
[patent_app_type] => utility
[patent_app_number] => 16/805341
[patent_app_country] => US
[patent_app_date] => 2020-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 9921
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16805341
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/805341 | Interposer, microelectronic device assembly including same and methods of fabrication | Feb 27, 2020 | Issued |
Array
(
[id] => 16081007
[patent_doc_number] => 20200194490
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-18
[patent_title] => HIGH EFFICIENCY WIDE SPECTRUM SENSOR
[patent_app_type] => utility
[patent_app_number] => 16/801946
[patent_app_country] => US
[patent_app_date] => 2020-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8881
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16801946
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/801946 | High efficiency wide spectrum sensor | Feb 25, 2020 | Issued |
Array
(
[id] => 16081195
[patent_doc_number] => 20200194584
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-18
[patent_title] => VERTICAL SEMICONDUCTOR DEVICE WITH IMPROVED RUGGEDNESS
[patent_app_type] => utility
[patent_app_number] => 16/801260
[patent_app_country] => US
[patent_app_date] => 2020-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3924
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16801260
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/801260 | Vertical semiconductor device with improved ruggedness | Feb 25, 2020 | Issued |
Array
(
[id] => 16332353
[patent_doc_number] => 20200303319
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-24
[patent_title] => ISOLATED TRANSFORMER WITH INTEGRATED SHIELD TOPOLOGY FOR REDUCED EMI
[patent_app_type] => utility
[patent_app_number] => 16/800043
[patent_app_country] => US
[patent_app_date] => 2020-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8171
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16800043
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/800043 | Isolated transformer with integrated shield topology for reduced EMI | Feb 24, 2020 | Issued |
Array
(
[id] => 16080761
[patent_doc_number] => 20200194367
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-18
[patent_title] => MEMORY AND FABRICATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/799219
[patent_app_country] => US
[patent_app_date] => 2020-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3562
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799219
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/799219 | Memory and fabrication method thereof | Feb 23, 2020 | Issued |
Array
(
[id] => 17051284
[patent_doc_number] => 20210260718
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-26
[patent_title] => CHEMICAL MECHANICAL POLISHING USING FLUORESCENCE-BASED ENDPOINT DETECTION
[patent_app_type] => utility
[patent_app_number] => 16/797925
[patent_app_country] => US
[patent_app_date] => 2020-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6641
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16797925
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/797925 | CHEMICAL MECHANICAL POLISHING USING FLUORESCENCE-BASED ENDPOINT DETECTION | Feb 20, 2020 | Abandoned |
Array
(
[id] => 17566729
[patent_doc_number] => 20220130878
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-28
[patent_title] => DIODE ARRAY, ARRANGEMENT, AND SYSTEM
[patent_app_type] => utility
[patent_app_number] => 17/432800
[patent_app_country] => US
[patent_app_date] => 2020-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6323
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17432800
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/432800 | Diode array, arrangement, and system | Feb 19, 2020 | Issued |
Array
(
[id] => 17758125
[patent_doc_number] => 11398424
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-26
[patent_title] => Semiconductor package structure
[patent_app_type] => utility
[patent_app_number] => 16/793989
[patent_app_country] => US
[patent_app_date] => 2020-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 51
[patent_no_of_words] => 7126
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793989
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/793989 | Semiconductor package structure | Feb 17, 2020 | Issued |
Array
(
[id] => 16854050
[patent_doc_number] => 20210154795
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-05-27
[patent_title] => POLISHING HEAD FOR USE IN CHEMICAL MECHANICAL POLISHING AND CMP APPARATUS HAVING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/788098
[patent_app_country] => US
[patent_app_date] => 2020-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4108
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16788098
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/788098 | Polishing head for use in chemical mechanical polishing and CMP apparatus having the same | Feb 10, 2020 | Issued |
Array
(
[id] => 16001197
[patent_doc_number] => 20200176469
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-04
[patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/780935
[patent_app_country] => US
[patent_app_date] => 2020-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6819
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16780935
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/780935 | Method for manufacturing semiconductor memory device and semiconductor memory device | Feb 3, 2020 | Issued |
Array
(
[id] => 15969963
[patent_doc_number] => 20200168733
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-28
[patent_title] => HIGH VOLTAGE LATERAL JUNCTION DIODE DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/776544
[patent_app_country] => US
[patent_app_date] => 2020-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4615
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16776544
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/776544 | High voltage lateral junction diode device | Jan 29, 2020 | Issued |
Array
(
[id] => 17745709
[patent_doc_number] => 11393791
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-19
[patent_title] => Three-dimensional stacking semiconductor assemblies with near zero bond line thickness
[patent_app_type] => utility
[patent_app_number] => 16/774900
[patent_app_country] => US
[patent_app_date] => 2020-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 29
[patent_no_of_words] => 6666
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16774900
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/774900 | Three-dimensional stacking semiconductor assemblies with near zero bond line thickness | Jan 27, 2020 | Issued |
Array
(
[id] => 15969663
[patent_doc_number] => 20200168583
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-28
[patent_title] => SEMICONDUCTOR DEVICE PACKAGE INCLUDING EMBEDDED CONDUCTIVE ELEMENTS
[patent_app_type] => utility
[patent_app_number] => 16/774983
[patent_app_country] => US
[patent_app_date] => 2020-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5528
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16774983
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/774983 | Semiconductor device package including embedded conductive elements | Jan 27, 2020 | Issued |
Array
(
[id] => 15939133
[patent_doc_number] => 20200161200
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-21
[patent_title] => SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/751139
[patent_app_country] => US
[patent_app_date] => 2020-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6179
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16751139
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/751139 | Semiconductor package device and method of manufacturing the same | Jan 22, 2020 | Issued |
Array
(
[id] => 15939079
[patent_doc_number] => 20200161173
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-21
[patent_title] => CONTACT FORMATION METHOD AND RELATED STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 16/751136
[patent_app_country] => US
[patent_app_date] => 2020-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11414
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16751136
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/751136 | Contact formation method and related structure | Jan 22, 2020 | Issued |