Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14587879 [patent_doc_number] => 20190221548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => HYBRID BOND PAD STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/367720 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7453 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16367720 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/367720
Hybrid bond pad structure Mar 27, 2019 Issued
Array ( [id] => 19414818 [patent_doc_number] => 12080655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Method to implement wafer-level chip-scale packages with grounded conformal shield [patent_app_type] => utility [patent_app_number] => 16/368032 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 6594 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16368032 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/368032
Method to implement wafer-level chip-scale packages with grounded conformal shield Mar 27, 2019 Issued
Array ( [id] => 14587745 [patent_doc_number] => 20190221481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => Methods for Splitting Semiconductor Devices and Semiconductor Device [patent_app_type] => utility [patent_app_number] => 16/364878 [patent_app_country] => US [patent_app_date] => 2019-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6335 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16364878 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/364878
Methods for Splitting Semiconductor Devices and Semiconductor Device Mar 25, 2019 Abandoned
Array ( [id] => 15000021 [patent_doc_number] => 20190318968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/358810 [patent_app_country] => US [patent_app_date] => 2019-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358810 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358810
Semiconductor device and method of manufacturing the same Mar 19, 2019 Issued
Array ( [id] => 15873701 [patent_doc_number] => 20200144254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => INTEGRATED CIRCUIT DEVICES INCLUDING A VERTICAL FIELD-EFFECT TRANSISTOR (VFET) AND A FIN FIELD-EFFECT TRANSISTOR (FINFET) AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/358245 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358245 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358245
Integrated circuit devices including a vertical field-effect transistor (VFET) and a fin field-effect transistor (FinFET) and methods of forming the same Mar 18, 2019 Issued
Array ( [id] => 14573729 [patent_doc_number] => 20190214472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => MEMORY CELLS HAVING ELECTRICALLY CONDUCTIVE NANODOTS AND APPARATUS HAVING SUCH MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/357583 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16357583 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/357583
Memory cells having electrically conductive nanodots and apparatus having such memory cells Mar 18, 2019 Issued
Array ( [id] => 17270475 [patent_doc_number] => 11195905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-07 [patent_title] => Metal-oxide-semiconductor transistor and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 16/358556 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 3346 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358556 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358556
Metal-oxide-semiconductor transistor and method of fabricating the same Mar 18, 2019 Issued
Array ( [id] => 14904497 [patent_doc_number] => 20190296014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => Circuit Arrangement, Redistribution Board, Module and Method of Fabricating a Half-Bridge Circuit [patent_app_type] => utility [patent_app_number] => 16/358309 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358309 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358309
Circuit arrangement, redistribution board, module and method of fabricating a half-bridge circuit Mar 18, 2019 Issued
Array ( [id] => 16865817 [patent_doc_number] => 11024570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Semiconductor package device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/358378 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 6699 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358378 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358378
Semiconductor package device and method of manufacturing the same Mar 18, 2019 Issued
Array ( [id] => 16707905 [patent_doc_number] => 10957849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Magnetic tunnel junctions with coupling-pinning layer lattice matching [patent_app_type] => utility [patent_app_number] => 16/358475 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 14422 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358475 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358475
Magnetic tunnel junctions with coupling-pinning layer lattice matching Mar 18, 2019 Issued
Array ( [id] => 16653601 [patent_doc_number] => 10930794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Self-aligned spacers for multi-gate devices and method of fabrication thereof [patent_app_type] => utility [patent_app_number] => 16/358314 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 64 [patent_no_of_words] => 11703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358314 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358314
Self-aligned spacers for multi-gate devices and method of fabrication thereof Mar 18, 2019 Issued
Array ( [id] => 16789225 [patent_doc_number] => 10991664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Integrated fuse [patent_app_type] => utility [patent_app_number] => 16/358223 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2886 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358223 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358223
Integrated fuse Mar 18, 2019 Issued
Array ( [id] => 16332317 [patent_doc_number] => 20200303283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => FLEXIBLE BASE DESIGN FOR CHIPSET HEAT SINK [patent_app_type] => utility [patent_app_number] => 16/358250 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3037 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358250 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358250
Flexible base design for chipset heat sink Mar 18, 2019 Issued
Array ( [id] => 15503465 [patent_doc_number] => 20200051921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => INTEGRATED CIRCUIT DEVICES INCLUDING A BORON-CONTAINING INSULATING PATTERN [patent_app_type] => utility [patent_app_number] => 16/358212 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358212 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358212
Integrated circuit devices including a boron-containing insulating pattern Mar 18, 2019 Issued
Array ( [id] => 18387329 [patent_doc_number] => 11658122 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => EMIB patch on glass laminate substrate [patent_app_type] => utility [patent_app_number] => 16/356442 [patent_app_country] => US [patent_app_date] => 2019-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 6647 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16356442 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/356442
EMIB patch on glass laminate substrate Mar 17, 2019 Issued
Array ( [id] => 16699919 [patent_doc_number] => 10950527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/291872 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 8921 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291872 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291872
Semiconductor device and method for manufacturing the same Mar 3, 2019 Issued
Array ( [id] => 16410101 [patent_doc_number] => 10818666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Gate noble metal nanoparticles [patent_app_type] => utility [patent_app_number] => 16/291597 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7021 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291597 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291597
Gate noble metal nanoparticles Mar 3, 2019 Issued
Array ( [id] => 16301057 [patent_doc_number] => 20200286780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => FABRICATING VIAS WITH LOWER RESISTANCE [patent_app_type] => utility [patent_app_number] => 16/291463 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5894 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291463 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291463
Fabricating vias with lower resistance Mar 3, 2019 Issued
Array ( [id] => 16301182 [patent_doc_number] => 20200286905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => THREE-DIMENSIONAL DEVICE WITH BONDED STRUCTURES INCLUDING A SUPPORT DIE AND METHODS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/291577 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 41770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291577 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291577
Three-dimensional device with bonded structures including a support die and methods of making the same Mar 3, 2019 Issued
Array ( [id] => 15717871 [patent_doc_number] => 20200105703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => FAN-OUT SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/291621 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10825 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291621 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291621
Fan-out semiconductor package Mar 3, 2019 Issued
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