Search

Long Pham

Examiner (ID: 16756, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2899, 2897, 1107, 2814, 1763, 2812, 2822, 2823
Total Applications
3709
Issued Applications
3257
Pending Applications
178
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12990571 [patent_doc_number] => 20170345935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => METHOD TO FORM STRAINED CHANNEL IN THIN BOX SOI STRUCTURES BY ELASTIC STRAIN RELAXATION OF THE SUBSTRATE [patent_app_type] => utility [patent_app_number] => 15/677855 [patent_app_country] => US [patent_app_date] => 2017-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15677855 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/677855
Method to form strained channel in thin box SOI structures by elastic strain relaxation of the substrate Aug 14, 2017 Issued
Array ( [id] => 15108895 [patent_doc_number] => 10475779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP [patent_app_type] => utility [patent_app_number] => 15/676488 [patent_app_country] => US [patent_app_date] => 2017-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 107 [patent_no_of_words] => 35151 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15676488 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/676488
Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP Aug 13, 2017 Issued
Array ( [id] => 12054491 [patent_doc_number] => 20170330835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'EMBEDDED MULTI-DEVICE BRIDGE WITH THROUGH-BRIDGE CONDUCTIVE VIA SIGNAL CONNECTION' [patent_app_type] => utility [patent_app_number] => 15/668179 [patent_app_country] => US [patent_app_date] => 2017-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6181 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15668179 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/668179
Embedded multi-device bridge with through-bridge conductive via signal connection Aug 2, 2017 Issued
Array ( [id] => 14366425 [patent_doc_number] => 10304524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Semiconductor structure and memory device including the structure [patent_app_type] => utility [patent_app_number] => 15/630614 [patent_app_country] => US [patent_app_date] => 2017-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 4519 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15630614 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/630614
Semiconductor structure and memory device including the structure Jun 21, 2017 Issued
Array ( [id] => 15644757 [patent_doc_number] => 10595409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Electro-magnetic interference (EMI) shielding techniques and configurations [patent_app_type] => utility [patent_app_number] => 15/628430 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6616 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15628430 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/628430
Electro-magnetic interference (EMI) shielding techniques and configurations Jun 19, 2017 Issued
Array ( [id] => 14036495 [patent_doc_number] => 10230005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Four terminal stacked complementary junction field effect transistors [patent_app_type] => utility [patent_app_number] => 15/617665 [patent_app_country] => US [patent_app_date] => 2017-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 8830 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15617665 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/617665
Four terminal stacked complementary junction field effect transistors Jun 7, 2017 Issued
Array ( [id] => 14267827 [patent_doc_number] => 10283485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Semiconductor device including conductive bump interconnections [patent_app_type] => utility [patent_app_number] => 15/617867 [patent_app_country] => US [patent_app_date] => 2017-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 6085 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15617867 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/617867
Semiconductor device including conductive bump interconnections Jun 7, 2017 Issued
Array ( [id] => 13613461 [patent_doc_number] => 20180358280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => METHODS AND APPARATUS FOR THERMAL INTERFACE MATERIAL (TIM) BOND LINE THICKNESS (BLT) REDUCTION AND TIM ADHESION ENHANCEMENT FOR EFFICIENT THERMAL MANAGEMENT [patent_app_type] => utility [patent_app_number] => 15/617774 [patent_app_country] => US [patent_app_date] => 2017-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6147 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15617774 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/617774
Methods and apparatus for thermal interface material (TIM) bond line thickness (BLT) reduction and TIM adhesion enhancement for efficient thermal management Jun 7, 2017 Issued
Array ( [id] => 13392823 [patent_doc_number] => 20180247954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-30 [patent_title] => SEMICONDUCTOR DEVICE CONTAINING MULTILAYER TITANIUM NITRIDE DIFFUSION BARRIER AND METHOD OF MAKING THEREOF [patent_app_type] => utility [patent_app_number] => 15/617499 [patent_app_country] => US [patent_app_date] => 2017-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15617499 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/617499
Semiconductor device containing multilayer titanium nitride diffusion barrier and method of making thereof Jun 7, 2017 Issued
Array ( [id] => 14094297 [patent_doc_number] => 10243063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Method of uniform channel formation [patent_app_type] => utility [patent_app_number] => 15/617613 [patent_app_country] => US [patent_app_date] => 2017-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3310 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15617613 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/617613
Method of uniform channel formation Jun 7, 2017 Issued
Array ( [id] => 12823702 [patent_doc_number] => 20180166406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => SEMICONDUCTOR DEVICE HAVING A PASSIVATION LAYER AND METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 15/617405 [patent_app_country] => US [patent_app_date] => 2017-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15617405 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/617405
Semiconductor device having a passivation layer and method of making the same Jun 7, 2017 Issued
Array ( [id] => 13862381 [patent_doc_number] => 10192916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-29 [patent_title] => Methods of fabricating solid-state imaging devices having flat microlenses [patent_app_type] => utility [patent_app_number] => 15/617523 [patent_app_country] => US [patent_app_date] => 2017-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4823 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15617523 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/617523
Methods of fabricating solid-state imaging devices having flat microlenses Jun 7, 2017 Issued
Array ( [id] => 13121667 [patent_doc_number] => 10079189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-18 [patent_title] => P-type transparent conducting nickel oxide alloys [patent_app_type] => utility [patent_app_number] => 15/617339 [patent_app_country] => US [patent_app_date] => 2017-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8063 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15617339 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/617339
P-type transparent conducting nickel oxide alloys Jun 7, 2017 Issued
Array ( [id] => 13201733 [patent_doc_number] => 10115787 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-30 [patent_title] => Low leakage FET [patent_app_type] => utility [patent_app_number] => 15/616811 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 8719 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616811 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/616811
Low leakage FET Jun 6, 2017 Issued
Array ( [id] => 13283241 [patent_doc_number] => 10153211 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-11 [patent_title] => Methods, apparatus, and system for fabricating finFET devices with increased breakdown voltage [patent_app_type] => utility [patent_app_number] => 15/616681 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616681 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/616681
Methods, apparatus, and system for fabricating finFET devices with increased breakdown voltage Jun 6, 2017 Issued
Array ( [id] => 13293731 [patent_doc_number] => 10158066 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-18 [patent_title] => Two pass MRAM dummy solution [patent_app_type] => utility [patent_app_number] => 15/616624 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3036 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616624 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/616624
Two pass MRAM dummy solution Jun 6, 2017 Issued
Array ( [id] => 12823537 [patent_doc_number] => 20180166351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 15/616908 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5220 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616908 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/616908
Semiconductor package and method of forming the same Jun 6, 2017 Issued
Array ( [id] => 13893421 [patent_doc_number] => 10199263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Semiconductor devices and methods of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/616334 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616334 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/616334
Semiconductor devices and methods of manufacturing the same Jun 6, 2017 Issued
Array ( [id] => 13613693 [patent_doc_number] => 20180358396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => SOLID-STATE IMAGING DEVICES HAVING A MICROLENS LAYER WITH DUMMY STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/616390 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5390 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616390 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/616390
Solid-state imaging devices having a microlens layer with dummy structures Jun 6, 2017 Issued
Array ( [id] => 13613685 [patent_doc_number] => 20180358392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => IMAGE SENSOR AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/616904 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616904 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/616904
IMAGE SENSOR AND FABRICATION METHOD THEREOF Jun 6, 2017 Abandoned
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