Long Pham

Array ( [id] => 15108877 [patent_doc_number] => 10475770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Semiconductor device having stacked dies and stacked pillars and method of manufacturing thereof [patent_app_type] => utility [patent_app_number] => 15/445568 [patent_app_country] => US [patent_app_date] => 2017-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 12425 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15445568 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13201575 [patent_doc_number] => 10115708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Semiconductor package having a redistribution line structure [patent_app_type] => utility [patent_app_number] => 15/443509 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7055 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13019721 [patent_doc_number] => 10032980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Integrated circuits with magnetic tunnel junctions and methods for producing the same [patent_app_type] => utility [patent_app_number] => 15/443799 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4710 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443799 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13228359 [patent_doc_number] => 10127958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Magnetic memory [patent_app_type] => utility [patent_app_number] => 15/443299 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7072 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443299 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12005658 [patent_doc_number] => 20170309813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-26 [patent_title] => 'INTEGRATED CIRCUITS WITH MAGNETIC TUNNEL JUNCTIONS AND METHODS FOR PRODUCING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/443741 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11952374 [patent_doc_number] => 20170256526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'TARGET INTEGRATED CIRCUIT COMBINED WITH A PLURALITY OF PHOTOVOLTAIC CELLS' [patent_app_type] => utility [patent_app_number] => 15/443473 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3509 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443473 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14525867 [patent_doc_number] => 10340204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Semiconductor devices having through electrodes and methods for fabricating the same [patent_app_type] => utility [patent_app_number] => 15/443259 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 4442 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443259 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13392917 [patent_doc_number] => 20180248001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-30 [patent_title] => SEGMENTED GUARD-RING AND CHIP EDGE SEALS [patent_app_type] => utility [patent_app_number] => 15/443276 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11963365 [patent_doc_number] => 20170267518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'PRESSURE SENSOR, PRODUCTION METHOD FOR PRESSURE SENSOR, ALTIMETER, ELECTRONIC APPARATUS, AND MOVING OBJECT' [patent_app_type] => utility [patent_app_number] => 15/443320 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10021 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11673949 [patent_doc_number] => 20170162673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'GATE-ALL-AROUND FIN DEVICE' [patent_app_type] => utility [patent_app_number] => 15/441364 [patent_app_country] => US [patent_app_date] => 2017-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3566 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15441364 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11673845 [patent_doc_number] => 20170162569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'GATE-ALL-AROUND FIN DEVICE' [patent_app_type] => utility [patent_app_number] => 15/441353 [patent_app_country] => US [patent_app_date] => 2017-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3567 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15441353 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13257263 [patent_doc_number] => 10141329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-27 [patent_title] => Method for manufacturing semiconductor memory device and semiconductor memory device [patent_app_type] => utility [patent_app_number] => 15/440025 [patent_app_country] => US [patent_app_date] => 2017-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 33 [patent_no_of_words] => 6836 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15440025 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12154707 [patent_doc_number] => 20180025971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'SIMULTANEOUS FORMATION OF LINER AND METAL CONDUCTOR' [patent_app_type] => utility [patent_app_number] => 15/437639 [patent_app_country] => US [patent_app_date] => 2017-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3648 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15437639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14252589 [patent_doc_number] => 10276501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Formation of liner and metal conductor [patent_app_type] => utility [patent_app_number] => 15/437772 [patent_app_country] => US [patent_app_date] => 2017-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5038 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15437772 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13228885 [patent_doc_number] => 10128225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Interconnect structures with polymer core [patent_app_type] => utility [patent_app_number] => 15/436291 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 12280 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15436291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11946006 [patent_doc_number] => 20170250156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'IMAGING SYSTEM AND MANUFACTURING APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/434489 [patent_app_country] => US [patent_app_date] => 2017-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 24905 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15434489 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16598143 [patent_doc_number] => 20210024674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => POLYMER COMPOUND, COMPOSITION, INSULATING LAYER, AND ORGANIC THIN FILM TRANSISTOR [patent_app_type] => utility [patent_app_number] => 15/999062 [patent_app_country] => US [patent_app_date] => 2017-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15999062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11673861 [patent_doc_number] => 20170162586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'SPLIT-GATE SEMICONDUCTOR DEVICE WITH L-SHAPED GATE' [patent_app_type] => utility [patent_app_number] => 15/433848 [patent_app_country] => US [patent_app_date] => 2017-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3559 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15433848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11666287 [patent_doc_number] => 20170155006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'EDGE PROTECTED BARRIER ASSEMBLIES' [patent_app_type] => utility [patent_app_number] => 15/429649 [patent_app_country] => US [patent_app_date] => 2017-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 9914 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15429649 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14036205 [patent_doc_number] => 10229858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Conductive paths through dielectric with a high aspect ratio for semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/427984 [patent_app_country] => US [patent_app_date] => 2017-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 6541 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15427984 [rel_patent_id] =>[rel_patent_doc_number] =>)