Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12823537 [patent_doc_number] => 20180166351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 15/616908 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5220 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616908 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/616908
Semiconductor package and method of forming the same Jun 6, 2017 Issued
Array ( [id] => 13613685 [patent_doc_number] => 20180358392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => IMAGE SENSOR AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/616904 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616904 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/616904
IMAGE SENSOR AND FABRICATION METHOD THEREOF Jun 6, 2017 Abandoned
Array ( [id] => 13893421 [patent_doc_number] => 10199263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Semiconductor devices and methods of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/616334 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616334 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/616334
Semiconductor devices and methods of manufacturing the same Jun 6, 2017 Issued
Array ( [id] => 13293731 [patent_doc_number] => 10158066 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-18 [patent_title] => Two pass MRAM dummy solution [patent_app_type] => utility [patent_app_number] => 15/616624 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3036 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616624 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/616624
Two pass MRAM dummy solution Jun 6, 2017 Issued
Array ( [id] => 13283241 [patent_doc_number] => 10153211 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-11 [patent_title] => Methods, apparatus, and system for fabricating finFET devices with increased breakdown voltage [patent_app_type] => utility [patent_app_number] => 15/616681 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616681 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/616681
Methods, apparatus, and system for fabricating finFET devices with increased breakdown voltage Jun 6, 2017 Issued
Array ( [id] => 14011623 [patent_doc_number] => 10224287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Semiconductor device and wafer level package including such semiconductor device [patent_app_type] => utility [patent_app_number] => 15/613144 [patent_app_country] => US [patent_app_date] => 2017-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3178 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15613144 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/613144
Semiconductor device and wafer level package including such semiconductor device Jun 2, 2017 Issued
Array ( [id] => 11952521 [patent_doc_number] => 20170256672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'Group III Nitride Heterostructure for Optoelectronic Device' [patent_app_type] => utility [patent_app_number] => 15/602677 [patent_app_country] => US [patent_app_date] => 2017-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10491 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15602677 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/602677
Group III nitride heterostructure for optoelectronic device May 22, 2017 Issued
Array ( [id] => 13207789 [patent_doc_number] => 10118247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Method for bonding wafers [patent_app_type] => utility [patent_app_number] => 15/599714 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4698 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15599714 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/599714
Method for bonding wafers May 18, 2017 Issued
Array ( [id] => 13085065 [patent_doc_number] => 10062605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-28 [patent_title] => Via and chamfer control for advanced interconnects [patent_app_type] => utility [patent_app_number] => 15/589229 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6412 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15589229 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/589229
Via and chamfer control for advanced interconnects May 7, 2017 Issued
Array ( [id] => 13528215 [patent_doc_number] => 20180315650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => PROCESS INTEGRATION APPROACH OF SELECTIVE TUNGSTEN VIA FILL [patent_app_type] => utility [patent_app_number] => 15/498024 [patent_app_country] => US [patent_app_date] => 2017-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15498024 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/498024
Process integration approach of selective tungsten via fill Apr 25, 2017 Issued
Array ( [id] => 13283317 [patent_doc_number] => 10153249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Dual-sided integrated fan-out package [patent_app_type] => utility [patent_app_number] => 15/482429 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 5885 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15482429 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/482429
Dual-sided integrated fan-out package Apr 6, 2017 Issued
Array ( [id] => 14707441 [patent_doc_number] => 10381483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Gate-all-around fin device [patent_app_type] => utility [patent_app_number] => 15/474078 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3461 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15474078 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/474078
Gate-all-around fin device Mar 29, 2017 Issued
Array ( [id] => 13271471 [patent_doc_number] => 10147822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Gate-all-around fin device [patent_app_type] => utility [patent_app_number] => 15/474055 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3457 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15474055 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/474055
Gate-all-around fin device Mar 29, 2017 Issued
Array ( [id] => 11824793 [patent_doc_number] => 20170213730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'METHOD AND STRUCTURE FOR FORMING DIELECTRIC ISOLATED FINFET WITH IMPROVED SOURCE/DRAIN EPITAXY' [patent_app_type] => utility [patent_app_number] => 15/464817 [patent_app_country] => US [patent_app_date] => 2017-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6381 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15464817 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/464817
Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy Mar 20, 2017 Issued
Array ( [id] => 12102161 [patent_doc_number] => 09859261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Photo-sensitive silicon package embedding self-powered electronic system' [patent_app_type] => utility [patent_app_number] => 15/465455 [patent_app_country] => US [patent_app_date] => 2017-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6817 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15465455 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/465455
Photo-sensitive silicon package embedding self-powered electronic system Mar 20, 2017 Issued
Array ( [id] => 11718406 [patent_doc_number] => 20170186906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'DIODE HAVING HIGH BRIGHTNESS AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/457655 [patent_app_country] => US [patent_app_date] => 2017-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4144 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15457655 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/457655
Diode having high brightness and method thereof Mar 12, 2017 Issued
Array ( [id] => 16034985 [patent_doc_number] => 10679925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Adhesive for semiconductor mounting, and semiconductor sensor [patent_app_type] => utility [patent_app_number] => 16/082430 [patent_app_country] => US [patent_app_date] => 2017-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 6164 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16082430 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/082430
Adhesive for semiconductor mounting, and semiconductor sensor Mar 9, 2017 Issued
Array ( [id] => 14043791 [patent_doc_number] => 20190078002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => ADHESIVE FOR SEMICONDUCTOR SENSOR CHIP MOUNTING, AND SEMICONDUCTOR SENSOR [patent_app_type] => utility [patent_app_number] => 16/082491 [patent_app_country] => US [patent_app_date] => 2017-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16082491 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/082491
Adhesive for semiconductor sensor chip mounting, and semiconductor sensor Mar 9, 2017 Issued
Array ( [id] => 14492261 [patent_doc_number] => 10332931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Semiconductor device for wafer-scale integration [patent_app_type] => utility [patent_app_number] => 15/455055 [patent_app_country] => US [patent_app_date] => 2017-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1952 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15455055 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/455055
Semiconductor device for wafer-scale integration Mar 8, 2017 Issued
Array ( [id] => 13293631 [patent_doc_number] => 10158016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => MOS devices with non-uniform p-type impurity profile [patent_app_type] => utility [patent_app_number] => 15/450265 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450265 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/450265
MOS devices with non-uniform p-type impurity profile Mar 5, 2017 Issued
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