Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12716635 [patent_doc_number] => 20180130711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => SEMICONDUCTOR FIN LOOP FOR USE WITH DIFFUSION BREAK [patent_app_type] => utility [patent_app_number] => 15/345612 [patent_app_country] => US [patent_app_date] => 2016-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15345612 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/345612
Semiconductor fin loop for use with diffusion break Nov 7, 2016 Issued
Array ( [id] => 12574035 [patent_doc_number] => 10020273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-10 [patent_title] => Semiconductor devices and methods of forming the same [patent_app_type] => utility [patent_app_number] => 15/345614 [patent_app_country] => US [patent_app_date] => 2016-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 7723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15345614 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/345614
Semiconductor devices and methods of forming the same Nov 7, 2016 Issued
Array ( [id] => 14151629 [patent_doc_number] => 10256204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Separation of integrated circuit structure from adjacent chip [patent_app_type] => utility [patent_app_number] => 15/345608 [patent_app_country] => US [patent_app_date] => 2016-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6024 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15345608 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/345608
Separation of integrated circuit structure from adjacent chip Nov 7, 2016 Issued
Array ( [id] => 12334659 [patent_doc_number] => 09947554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Support substrate and a method of manufacturing a semiconductor package using the same [patent_app_type] => utility [patent_app_number] => 15/345534 [patent_app_country] => US [patent_app_date] => 2016-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 6083 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15345534 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/345534
Support substrate and a method of manufacturing a semiconductor package using the same Nov 7, 2016 Issued
Array ( [id] => 13019271 [patent_doc_number] => 10032755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Power semiconductor arrangement having a plurality of power semiconductor switching elements and reduced inductance asymmetry [patent_app_type] => utility [patent_app_number] => 15/345751 [patent_app_country] => US [patent_app_date] => 2016-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4582 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15345751 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/345751
Power semiconductor arrangement having a plurality of power semiconductor switching elements and reduced inductance asymmetry Nov 7, 2016 Issued
Array ( [id] => 11502809 [patent_doc_number] => 20170076994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'STRUCTURE AND FORMATION METHOD OF FIN-LIKE FIELD EFFECT TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 15/345279 [patent_app_country] => US [patent_app_date] => 2016-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15345279 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/345279
Structure and formation method of fin-like field effect transistor Nov 6, 2016 Issued
Array ( [id] => 12174887 [patent_doc_number] => 09893035 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-13 [patent_title] => 'Stacked package structure and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 15/345490 [patent_app_country] => US [patent_app_date] => 2016-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5618 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15345490 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/345490
Stacked package structure and manufacturing method thereof Nov 6, 2016 Issued
Array ( [id] => 12778942 [patent_doc_number] => 20180151482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => ELECTRONIC DEVICE, MANUFACTURING METHOD AND LEAD FRAME FOR SAME [patent_app_type] => utility [patent_app_number] => 15/345478 [patent_app_country] => US [patent_app_date] => 2016-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5417 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15345478 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/345478
ELECTRONIC DEVICE, MANUFACTURING METHOD AND LEAD FRAME FOR SAME Nov 6, 2016 Abandoned
Array ( [id] => 13950879 [patent_doc_number] => 10211218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => U-shaped vertical thin-channel memory [patent_app_type] => utility [patent_app_number] => 15/344899 [patent_app_country] => US [patent_app_date] => 2016-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 30 [patent_no_of_words] => 14538 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15344899 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/344899
U-shaped vertical thin-channel memory Nov 6, 2016 Issued
Array ( [id] => 12047456 [patent_doc_number] => 09825065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-21 [patent_title] => 'Thin film transistor array substrate and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 15/342756 [patent_app_country] => US [patent_app_date] => 2016-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 7535 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15342756 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/342756
Thin film transistor array substrate and manufacturing method thereof Nov 2, 2016 Issued
Array ( [id] => 16256872 [patent_doc_number] => 20200266247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => MOTHER BOARD, AND METHOD FOR MANUFACTURING LIGHTING DEVICE [patent_app_type] => utility [patent_app_number] => 16/067895 [patent_app_country] => US [patent_app_date] => 2016-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16067895 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/067895
MOTHER BOARD, AND METHOD FOR MANUFACTURING LIGHTING DEVICE Oct 30, 2016 Abandoned
Array ( [id] => 16293812 [patent_doc_number] => 10770670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Inverted organic photosensitive devices [patent_app_type] => utility [patent_app_number] => 15/332062 [patent_app_country] => US [patent_app_date] => 2016-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 10076 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15332062 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/332062
Inverted organic photosensitive devices Oct 23, 2016 Issued
Array ( [id] => 11439413 [patent_doc_number] => 20170040433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'SEMICONDUCTOR DEVICE FOR COMPENSATING INTERNAL DELAY, METHODS THEREOF, AND DATA PROCESSING SYSTEM HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/299864 [patent_app_country] => US [patent_app_date] => 2016-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4025 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15299864 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/299864
Semiconductor device for compensating internal delay, methods thereof, and data processing system having the same Oct 20, 2016 Issued
Array ( [id] => 11424873 [patent_doc_number] => 20170033019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/294797 [patent_app_country] => US [patent_app_date] => 2016-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3063 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15294797 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/294797
Semiconductor device and method for fabricating the same Oct 16, 2016 Issued
Array ( [id] => 11701736 [patent_doc_number] => 09691659 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-06-27 [patent_title] => 'Via and chamfer control for advanced interconnects' [patent_app_type] => utility [patent_app_number] => 15/282012 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6493 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15282012 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/282012
Via and chamfer control for advanced interconnects Sep 29, 2016 Issued
Array ( [id] => 17100183 [patent_doc_number] => 20210287974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => METHODS OF UTILIZING LOW TEMPERATURE SOLDER ASSISTED MOUNTING TECHNIQUES FOR PACKAGE STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/328617 [patent_app_country] => US [patent_app_date] => 2016-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6423 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16328617 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/328617
Methods of utilizing low temperature solder assisted mounting techniques for package structures Sep 28, 2016 Issued
Array ( [id] => 11424868 [patent_doc_number] => 20170033014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'SEMICONDUCTOR DEVICE AND FORMATION THEREOF' [patent_app_type] => utility [patent_app_number] => 15/270207 [patent_app_country] => US [patent_app_date] => 2016-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6428 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270207 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/270207
Semiconductor device and formation thereof Sep 19, 2016 Issued
Array ( [id] => 12535128 [patent_doc_number] => 10008569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-26 [patent_title] => Semiconductor device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 15/259060 [patent_app_country] => US [patent_app_date] => 2016-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3160 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15259060 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/259060
Semiconductor device and method for fabricating the same Sep 7, 2016 Issued
Array ( [id] => 14827853 [patent_doc_number] => 10410941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Wafer level semiconductor device with wettable flanks [patent_app_type] => utility [patent_app_number] => 15/259063 [patent_app_country] => US [patent_app_date] => 2016-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 27 [patent_no_of_words] => 2739 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15259063 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/259063
Wafer level semiconductor device with wettable flanks Sep 7, 2016 Issued
Array ( [id] => 11824903 [patent_doc_number] => 20170213840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 15/258774 [patent_app_country] => US [patent_app_date] => 2016-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 12586 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15258774 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/258774
Semiconductor device and method for manufacturing same Sep 6, 2016 Issued
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