Long Pham

Array ( [id] => 12047462 [patent_doc_number] => 09825071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-21 [patent_title] => 'Light detection device' [patent_app_type] => utility [patent_app_number] => 15/207569 [patent_app_country] => US [patent_app_date] => 2016-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5791 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15207569 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12435393 [patent_doc_number] => 09978313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-22 [patent_title] => Organic light emitting diode display, driving method thereof, and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/205892 [patent_app_country] => US [patent_app_date] => 2016-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 10773 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15205892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12872659 [patent_doc_number] => 20180182728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MAKING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/739283 [patent_app_country] => US [patent_app_date] => 2016-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15739283 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13131927 [patent_doc_number] => 10083903 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-25 [patent_title] => Integrated circuit packaging system with molded laser via interposer and method of manufacture thereof [patent_app_type] => utility [patent_app_number] => 15/201575 [patent_app_country] => US [patent_app_date] => 2016-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 7535 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15201575 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11847536 [patent_doc_number] => 09735094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'Combined packaged power semiconductor device' [patent_app_type] => utility [patent_app_number] => 15/193000 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 6859 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12953368 [patent_doc_number] => 09837265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-05 [patent_title] => Gas flow profile modulated control of overlay in plasma CVD films [patent_app_type] => utility [patent_app_number] => 15/192732 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 6625 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192732 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12175031 [patent_doc_number] => 09893179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Method for producing semiconductor device and semiconductor device' [patent_app_type] => utility [patent_app_number] => 15/191712 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 138 [patent_no_of_words] => 9980 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15191712 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11353589 [patent_doc_number] => 20160372329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'Methods for Forming a Semiconductor Device and a Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 15/178039 [patent_app_country] => US [patent_app_date] => 2016-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15178039 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11087884 [patent_doc_number] => 20160284852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'GATE-ALL-AROUND FIN DEVICE' [patent_app_type] => utility [patent_app_number] => 15/171288 [patent_app_country] => US [patent_app_date] => 2016-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3566 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15171288 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11471032 [patent_doc_number] => 20170057814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'MEMS AND CMOS INTEGRATION WITH LOW-TEMPERATURE BONDING' [patent_app_type] => utility [patent_app_number] => 15/170154 [patent_app_country] => US [patent_app_date] => 2016-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7739 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15170154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11079475 [patent_doc_number] => 20160276439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'OUTPUT CAPACITANCE REDUCTION IN POWER TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 15/169777 [patent_app_country] => US [patent_app_date] => 2016-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13698 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15169777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11071207 [patent_doc_number] => 20160268170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF' [patent_app_type] => utility [patent_app_number] => 15/160257 [patent_app_country] => US [patent_app_date] => 2016-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4262 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15160257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11043532 [patent_doc_number] => 20160240488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'SEMICONDUCTOR DEVICE WITH AN ISOLATION STRUCTURE COUPLED TO A COVER OF THE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/136326 [patent_app_country] => US [patent_app_date] => 2016-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7170 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15136326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13201595 [patent_doc_number] => 10115718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Method, apparatus, and system for metal-oxide-semiconductor field-effect transistor (MOSFET) with electrostatic discharge (ESD) protection [patent_app_type] => utility [patent_app_number] => 15/134942 [patent_app_country] => US [patent_app_date] => 2016-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 6189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15134942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12012868 [patent_doc_number] => 09806192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-31 [patent_title] => 'Suppression of back-gate transistors in RF CMOS switches built on an SOI substrate' [patent_app_type] => utility [patent_app_number] => 15/133669 [patent_app_country] => US [patent_app_date] => 2016-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15133669 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12005491 [patent_doc_number] => 20170309647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-26 [patent_title] => 'STRUCTURE AND METHOD TO FORM DEFECT FREE HIGH-MOBILITY SEMICONDUCTOR FINS ON INSULATOR' [patent_app_type] => utility [patent_app_number] => 15/134083 [patent_app_country] => US [patent_app_date] => 2016-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7109 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15134083 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11021088 [patent_doc_number] => 20160218042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'Nonplanar Device and Strain-Generating Channel Dielectric' [patent_app_type] => utility [patent_app_number] => 15/088278 [patent_app_country] => US [patent_app_date] => 2016-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7380 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15088278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17438988 [patent_doc_number] => 11264329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Semiconductor device having metal interconnects with different thicknesses [patent_app_type] => utility [patent_app_number] => 16/074142 [patent_app_country] => US [patent_app_date] => 2016-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5303 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16074142 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12263947 [patent_doc_number] => 20180083143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/561996 [patent_app_country] => US [patent_app_date] => 2016-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 14841 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15561996 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11050924 [patent_doc_number] => 20160247883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'EPITAXIAL SILICON GERMANIUM FIN FORMATION USING SACRIFICIAL SILICON FIN TEMPLATES' [patent_app_type] => utility [patent_app_number] => 15/078024 [patent_app_country] => US [patent_app_date] => 2016-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2794 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15078024 [rel_patent_id] =>[rel_patent_doc_number] =>)