Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12263959 [patent_doc_number] => 20180083156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'LIGHT EMITTING DIODE CHIP AND A METHOD FOR THE MANUFACTURE OF A LIGHT EMITTING DIODE CHIP' [patent_app_type] => utility [patent_app_number] => 15/558603 [patent_app_country] => US [patent_app_date] => 2016-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7876 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15558603 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/558603
Light emitting diode chip and a method for the manufacture of a light emitting diode chip Mar 15, 2016 Issued
Array ( [id] => 11959613 [patent_doc_number] => 20170263765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'DRIFT-REGION FIELD CONTROL OF AN LDMOS TRANSISTOR USING BIASED SHALLOW-TRENCH FIELD PLATES' [patent_app_type] => utility [patent_app_number] => 15/065280 [patent_app_country] => US [patent_app_date] => 2016-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5228 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15065280 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/065280
Drift-region field control of an LDMOS transistor using biased shallow-trench field plates Mar 8, 2016 Issued
Array ( [id] => 13056951 [patent_doc_number] => 10049872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Method for growing epitaxies of a chemical compound semiconductor [patent_app_type] => utility [patent_app_number] => 15/063572 [patent_app_country] => US [patent_app_date] => 2016-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15063572 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/063572
Method for growing epitaxies of a chemical compound semiconductor Mar 7, 2016 Issued
Array ( [id] => 11696262 [patent_doc_number] => 20170171979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'InFO Coil on Metal Plate with Slot' [patent_app_type] => utility [patent_app_number] => 15/061419 [patent_app_country] => US [patent_app_date] => 2016-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5582 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15061419 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/061419
InFO coil on metal plate with slot Mar 3, 2016 Issued
Array ( [id] => 14011815 [patent_doc_number] => 10224384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Display [patent_app_type] => utility [patent_app_number] => 15/060682 [patent_app_country] => US [patent_app_date] => 2016-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2471 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15060682 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/060682
Display Mar 3, 2016 Issued
Array ( [id] => 12936430 [patent_doc_number] => 09831377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-28 [patent_title] => Die-cutting approaches for foil-based metallization of solar cells [patent_app_type] => utility [patent_app_number] => 15/055912 [patent_app_country] => US [patent_app_date] => 2016-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 6494 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15055912 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/055912
Die-cutting approaches for foil-based metallization of solar cells Feb 28, 2016 Issued
Array ( [id] => 13188175 [patent_doc_number] => 10109614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-23 [patent_title] => Silicon package for embedded electronic system having stacked semiconductor chips [patent_app_type] => utility [patent_app_number] => 15/053089 [patent_app_country] => US [patent_app_date] => 2016-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6001 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15053089 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/053089
Silicon package for embedded electronic system having stacked semiconductor chips Feb 24, 2016 Issued
Array ( [id] => 10984476 [patent_doc_number] => 20160181421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'SEMICONDUCTOR DEVICES AND RELATED FABRICATION METHODS' [patent_app_type] => utility [patent_app_number] => 15/053745 [patent_app_country] => US [patent_app_date] => 2016-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12573 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15053745 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/053745
Semiconductor devices and related fabrication methods Feb 24, 2016 Issued
Array ( [id] => 13201743 [patent_doc_number] => 10115792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Semiconductor device and method of manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 15/041012 [patent_app_country] => US [patent_app_date] => 2016-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 10181 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15041012 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/041012
Semiconductor device and method of manufacturing semiconductor device Feb 9, 2016 Issued
Array ( [id] => 14429781 [patent_doc_number] => 10319704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Semiconductor module [patent_app_type] => utility [patent_app_number] => 15/739424 [patent_app_country] => US [patent_app_date] => 2016-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 9907 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15739424 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/739424
Semiconductor module Jan 30, 2016 Issued
Array ( [id] => 10802735 [patent_doc_number] => 20160148892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'SOLDER IN CAVITY INTERCONNECTION STRUCTURES' [patent_app_type] => utility [patent_app_number] => 15/009206 [patent_app_country] => US [patent_app_date] => 2016-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4319 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15009206 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/009206
SOLDER IN CAVITY INTERCONNECTION STRUCTURES Jan 27, 2016 Abandoned
Array ( [id] => 11201107 [patent_doc_number] => 09431328 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-30 [patent_title] => 'Power device and preparation method thereof' [patent_app_type] => utility [patent_app_number] => 15/007670 [patent_app_country] => US [patent_app_date] => 2016-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3921 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15007670 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/007670
Power device and preparation method thereof Jan 26, 2016 Issued
Array ( [id] => 11524533 [patent_doc_number] => 09607944 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-28 [patent_title] => 'Efficient layout placement of a diode' [patent_app_type] => utility [patent_app_number] => 15/006667 [patent_app_country] => US [patent_app_date] => 2016-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3827 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15006667 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/006667
Efficient layout placement of a diode Jan 25, 2016 Issued
Array ( [id] => 11111034 [patent_doc_number] => 20160308004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'SEMICONDUCTOR DEVICES INCLUDING CONTACT STRUCTURES THAT PARTIALLY OVERLAP SILICIDE LAYERS' [patent_app_type] => utility [patent_app_number] => 15/006717 [patent_app_country] => US [patent_app_date] => 2016-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 10625 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15006717 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/006717
Semiconductor devices including contact structures that partially overlap silicide layers Jan 25, 2016 Issued
Array ( [id] => 11028752 [patent_doc_number] => 20160225708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/006306 [patent_app_country] => US [patent_app_date] => 2016-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 7974 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15006306 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/006306
Semiconductor substrate and manufacturing method thereof Jan 25, 2016 Issued
Array ( [id] => 11510348 [patent_doc_number] => 09601514 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-21 [patent_title] => 'Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy' [patent_app_type] => utility [patent_app_number] => 15/006284 [patent_app_country] => US [patent_app_date] => 2016-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 6381 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15006284 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/006284
Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy Jan 25, 2016 Issued
Array ( [id] => 11821675 [patent_doc_number] => 20170210612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'ROUGH ANTI-STICTION LAYER FOR MEMS DEVICE' [patent_app_type] => utility [patent_app_number] => 15/006301 [patent_app_country] => US [patent_app_date] => 2016-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5709 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15006301 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/006301
Rough anti-stiction layer for MEMS device Jan 25, 2016 Issued
Array ( [id] => 11346484 [patent_doc_number] => 09530900 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-27 [patent_title] => 'Schottky diode and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 15/006579 [patent_app_country] => US [patent_app_date] => 2016-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2327 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15006579 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/006579
Schottky diode and method for manufacturing the same Jan 25, 2016 Issued
Array ( [id] => 11824861 [patent_doc_number] => 20170213798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'FORMING LARGE CHIPS THROUGH STITCHING' [patent_app_type] => utility [patent_app_number] => 15/006838 [patent_app_country] => US [patent_app_date] => 2016-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 5587 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15006838 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/006838
Forming large chips through stitching Jan 25, 2016 Issued
Array ( [id] => 11925627 [patent_doc_number] => 09793216 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Fabrication of IC structure with metal plug' [patent_app_type] => utility [patent_app_number] => 15/006426 [patent_app_country] => US [patent_app_date] => 2016-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5863 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15006426 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/006426
Fabrication of IC structure with metal plug Jan 25, 2016 Issued
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