Search

Long Pham

Examiner (ID: 5269, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2822, 2899, 2897, 2823, 1107, 2814, 2812, 1763
Total Applications
3774
Issued Applications
3306
Pending Applications
160
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15139285 [patent_doc_number] => 10483128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Epitaxially coated semiconductor wafer, and method for producing an epitaxially coated semiconductor wafer [patent_app_type] => utility [patent_app_number] => 15/545541 [patent_app_country] => US [patent_app_date] => 2015-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3571 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15545541 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/545541
Epitaxially coated semiconductor wafer, and method for producing an epitaxially coated semiconductor wafer Oct 28, 2015 Issued
Array ( [id] => 10689843 [patent_doc_number] => 20160035989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'HYBRID JUNCTION FIELD-EFFECT TRANSISTOR AND ACTIVE MATRIX STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/884744 [patent_app_country] => US [patent_app_date] => 2015-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10505 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14884744 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/884744
Hybrid junction field-effect transistor and active matrix structure Oct 14, 2015 Issued
Array ( [id] => 10689679 [patent_doc_number] => 20160035825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'SUPER JUNCTION SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/882606 [patent_app_country] => US [patent_app_date] => 2015-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6962 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14882606 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/882606
Super junction semiconductor device and method for manufacturing the same Oct 13, 2015 Issued
Array ( [id] => 10795207 [patent_doc_number] => 20160141365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'GATE-ALL-AROUND FIN DEVICE' [patent_app_type] => utility [patent_app_number] => 14/882809 [patent_app_country] => US [patent_app_date] => 2015-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3569 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14882809 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/882809
Gate-all-around fin device Oct 13, 2015 Issued
Array ( [id] => 10984216 [patent_doc_number] => 20160181162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'GATE-ALL-AROUND FIN DEVICE' [patent_app_type] => utility [patent_app_number] => 14/882800 [patent_app_country] => US [patent_app_date] => 2015-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3567 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14882800 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/882800
Gate-all-around fin device Oct 13, 2015 Issued
Array ( [id] => 11557561 [patent_doc_number] => 20170103808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-13 [patent_title] => 'PLANAR VARIABLE RESISTANCE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/882147 [patent_app_country] => US [patent_app_date] => 2015-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9820 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14882147 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/882147
Planar variable resistance memory Oct 12, 2015 Issued
Array ( [id] => 11404793 [patent_doc_number] => 20170025331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-26 [patent_title] => 'LEAD FRAME, SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING LEAD FRAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/124472 [patent_app_country] => US [patent_app_date] => 2015-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4352 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15124472 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/124472
Lead frame, semiconductor device, method for manufacturing lead frame, and method for manufacturing semiconductor device Oct 5, 2015 Issued
Array ( [id] => 13392541 [patent_doc_number] => 20180247813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-30 [patent_title] => TECHNOLOGIES FOR INVERTING LITHOGRAPHIC PATTERNS AND SEMICONDUCTOR DEVICES INCLUDING HIGH ASPECT RATIO STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/755466 [patent_app_country] => US [patent_app_date] => 2015-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10633 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15755466 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/755466
Technologies for inverting lithographic patterns and semiconductor devices including high aspect ratio structures Sep 24, 2015 Issued
Array ( [id] => 11911148 [patent_doc_number] => 09779967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Ultra-thin power transistor and synchronous buck converter having customized footprint' [patent_app_type] => utility [patent_app_number] => 14/854140 [patent_app_country] => US [patent_app_date] => 2015-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6153 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14854140 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/854140
Ultra-thin power transistor and synchronous buck converter having customized footprint Sep 14, 2015 Issued
Array ( [id] => 10659562 [patent_doc_number] => 20160005706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES, METHODS OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/850875 [patent_app_country] => US [patent_app_date] => 2015-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7384 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14850875 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/850875
Semiconductor devices having through electrodes, methods of manufacturing the same, and semiconductor packages including the same Sep 9, 2015 Issued
Array ( [id] => 10795332 [patent_doc_number] => 20160141489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'TOPOLOGICAL METHOD TO BUILD SELF-ALIGNED MTJ WITHOUT A MASK' [patent_app_type] => utility [patent_app_number] => 14/841997 [patent_app_country] => US [patent_app_date] => 2015-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3549 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14841997 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/841997
Topological method to build self-aligned MTJ without a mask Aug 31, 2015 Issued
Array ( [id] => 11564727 [patent_doc_number] => 09627322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-18 [patent_title] => 'Semiconductor device having reduced contact resistance' [patent_app_type] => utility [patent_app_number] => 14/828639 [patent_app_country] => US [patent_app_date] => 2015-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3790 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14828639 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/828639
Semiconductor device having reduced contact resistance Aug 17, 2015 Issued
Array ( [id] => 10472449 [patent_doc_number] => 20150357465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'THRESHOLD VOLTAGE ADJUSTMENT OF A TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/828000 [patent_app_country] => US [patent_app_date] => 2015-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14828000 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/828000
Threshold voltage adjustment of a transistor Aug 16, 2015 Issued
Array ( [id] => 11246580 [patent_doc_number] => 09472631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-18 [patent_title] => 'Flexible active matrix circuits for interfacing with biological tissue' [patent_app_type] => utility [patent_app_number] => 14/827256 [patent_app_country] => US [patent_app_date] => 2015-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5258 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14827256 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/827256
Flexible active matrix circuits for interfacing with biological tissue Aug 13, 2015 Issued
Array ( [id] => 10472369 [patent_doc_number] => 20150357386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'HYBRID BIPOLAR JUNCTION TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/827266 [patent_app_country] => US [patent_app_date] => 2015-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6946 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14827266 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/827266
Hybrid bipolar junction transistor Aug 13, 2015 Issued
Array ( [id] => 10638436 [patent_doc_number] => 09355946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-31 [patent_title] => 'Converter having partially thinned leadframe with stacked chips and interposer, free of wires and clips' [patent_app_type] => utility [patent_app_number] => 14/823487 [patent_app_country] => US [patent_app_date] => 2015-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4818 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14823487 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/823487
Converter having partially thinned leadframe with stacked chips and interposer, free of wires and clips Aug 10, 2015 Issued
Array ( [id] => 10472251 [patent_doc_number] => 20150357267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'COMBINED PACKAGED POWER SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/823908 [patent_app_country] => US [patent_app_date] => 2015-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6726 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14823908 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/823908
Combined packaged power semiconductor device Aug 10, 2015 Issued
Array ( [id] => 11411896 [patent_doc_number] => 09559212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/810700 [patent_app_country] => US [patent_app_date] => 2015-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 52 [patent_no_of_words] => 29067 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14810700 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/810700
Semiconductor device and method for manufacturing the same Jul 27, 2015 Issued
Array ( [id] => 11904274 [patent_doc_number] => 09773714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Semiconductor package resin composition and usage method thereof' [patent_app_type] => utility [patent_app_number] => 14/810631 [patent_app_country] => US [patent_app_date] => 2015-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 10806 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14810631 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/810631
Semiconductor package resin composition and usage method thereof Jul 27, 2015 Issued
Array ( [id] => 10448203 [patent_doc_number] => 20150333217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-19 [patent_title] => 'DIODE HAVING HIGH BRIGHTNESS AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/807632 [patent_app_country] => US [patent_app_date] => 2015-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4146 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14807632 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/807632
Diode having high brightness and method thereof Jul 22, 2015 Issued
Menu