Search

Long Pham

Examiner (ID: 16756, Phone: (571)272-1714 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2899, 2897, 1107, 2814, 1763, 2812, 2822, 2823
Total Applications
3709
Issued Applications
3257
Pending Applications
178
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10850880 [patent_doc_number] => 08877559 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-04 [patent_title] => 'Through-silicon via with sidewall air gap' [patent_app_type] => utility [patent_app_number] => 13/853178 [patent_app_country] => US [patent_app_date] => 2013-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2106 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13853178 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/853178
Through-silicon via with sidewall air gap Mar 28, 2013 Issued
Array ( [id] => 9965413 [patent_doc_number] => 09013030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-21 [patent_title] => 'Leadframe, semiconductor package including a leadframe and method for producing a leadframe' [patent_app_type] => utility [patent_app_number] => 13/852058 [patent_app_country] => US [patent_app_date] => 2013-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4565 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13852058 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/852058
Leadframe, semiconductor package including a leadframe and method for producing a leadframe Mar 27, 2013 Issued
Array ( [id] => 9768117 [patent_doc_number] => 20140291779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'Semiconductor Devices and Methods for Manufacturing Semiconductor Devices' [patent_app_type] => utility [patent_app_number] => 13/851691 [patent_app_country] => US [patent_app_date] => 2013-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5025 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13851691 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/851691
Semiconductor devices and methods for manufacturing semiconductor devices Mar 26, 2013 Issued
Array ( [id] => 10876813 [patent_doc_number] => 08901603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-02 [patent_title] => 'Surge protection circuit for power MOSFETs used as active bypass diodes in photovoltaic solar power systems' [patent_app_type] => utility [patent_app_number] => 13/851253 [patent_app_country] => US [patent_app_date] => 2013-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2803 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13851253 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/851253
Surge protection circuit for power MOSFETs used as active bypass diodes in photovoltaic solar power systems Mar 26, 2013 Issued
Array ( [id] => 9460496 [patent_doc_number] => 20140124922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'BUMP STRUCTURES IN SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/846570 [patent_app_country] => US [patent_app_date] => 2013-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4230 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13846570 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/846570
Bump structures in semiconductor packages and methods of fabricating the same Mar 17, 2013 Issued
Array ( [id] => 9542634 [patent_doc_number] => 20140167281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'STACK TYPE SEMICONDUCTOR CIRCUIT WITH IMPEDANCE CALIBRATION' [patent_app_type] => utility [patent_app_number] => 13/845628 [patent_app_country] => US [patent_app_date] => 2013-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7608 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13845628 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/845628
Stack type semiconductor circuit with impedance calibration Mar 17, 2013 Issued
Array ( [id] => 10870167 [patent_doc_number] => 08895363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Die preparation for wafer-level chip scale package (WLCSP)' [patent_app_type] => utility [patent_app_number] => 13/833906 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2098 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13833906 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/833906
Die preparation for wafer-level chip scale package (WLCSP) Mar 14, 2013 Issued
Array ( [id] => 10870883 [patent_doc_number] => 08896083 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Depletion-mode field-effect transistor-based phototransitor' [patent_app_type] => utility [patent_app_number] => 13/835662 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 2859 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13835662 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/835662
Depletion-mode field-effect transistor-based phototransitor Mar 14, 2013 Issued
Array ( [id] => 9729185 [patent_doc_number] => 20140264892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'SEMICONDUCTOR DEVICE WITH DUMMY LINES' [patent_app_type] => utility [patent_app_number] => 13/840694 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3082 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13840694 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/840694
Semiconductor device with dummy lines Mar 14, 2013 Issued
Array ( [id] => 8960926 [patent_doc_number] => 20130200528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-08 [patent_title] => 'Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP' [patent_app_type] => utility [patent_app_number] => 13/832333 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 36801 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13832333 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/832333
Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP Mar 14, 2013 Issued
Array ( [id] => 9662200 [patent_doc_number] => 08809176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Replacement gate with reduced gate leakage current' [patent_app_type] => utility [patent_app_number] => 13/842217 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13842217 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/842217
Replacement gate with reduced gate leakage current Mar 14, 2013 Issued
Array ( [id] => 9488379 [patent_doc_number] => 20140138785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'PIXEL ISOLATION ELEMENTS, DEVICES, AND ASSOCIATED METHODS' [patent_app_type] => utility [patent_app_number] => 13/841120 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10210 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13841120 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/841120
Pixel isolation elements, devices, and associated methods Mar 14, 2013 Issued
Array ( [id] => 9729127 [patent_doc_number] => 20140264834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'Low Cost and Ultra-Thin Chip on Wafer on Substrate (CoWoS) Formation' [patent_app_type] => utility [patent_app_number] => 13/830570 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3092 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13830570 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/830570
Low cost and ultra-thin chip on wafer on substrate (CoWoS) formation Mar 13, 2013 Issued
Array ( [id] => 9729204 [patent_doc_number] => 20140264910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'INTERCONNECT STRUCTURES WITH POLYMER CORE' [patent_app_type] => utility [patent_app_number] => 13/829483 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12733 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13829483 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/829483
Interconnect structures with polymer core Mar 13, 2013 Issued
Array ( [id] => 9869118 [patent_doc_number] => 08956889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-17 [patent_title] => 'Method of testing through silicon VIAS (TSVs) of three dimensional integrated circuit (3DIC)' [patent_app_type] => utility [patent_app_number] => 13/800626 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 4802 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13800626 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/800626
Method of testing through silicon VIAS (TSVs) of three dimensional integrated circuit (3DIC) Mar 12, 2013 Issued
Array ( [id] => 9965295 [patent_doc_number] => 09012912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-21 [patent_title] => 'Wafers, panels, semiconductor devices, and glass treatment methods' [patent_app_type] => utility [patent_app_number] => 13/802484 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 5645 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13802484 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/802484
Wafers, panels, semiconductor devices, and glass treatment methods Mar 12, 2013 Issued
Array ( [id] => 9729250 [patent_doc_number] => 20140264957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'ROBUST INK FORMULATIONS FOR DURABLE MARKINGS ON MICROELECTRONIC PACKAGES AND ITS EXTENDIBILITY AS A BARRIER MATERIAL FOR THERMAL AND SEALANT MATERIALS' [patent_app_type] => utility [patent_app_number] => 13/801059 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3664 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13801059 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/801059
Robust ink formulations for durable markings on microelectronic packages and its extendibility as a barrier material for thermal and sealant materials Mar 12, 2013 Issued
Array ( [id] => 9729235 [patent_doc_number] => 20140264942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'SEMICONDUCTOR DEVICE CHANNELS' [patent_app_type] => utility [patent_app_number] => 13/795721 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2430 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13795721 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/795721
Semiconductor device channels Mar 11, 2013 Issued
Array ( [id] => 9729245 [patent_doc_number] => 20140264952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'SUPPLEMENTING WIRE BONDS' [patent_app_type] => utility [patent_app_number] => 13/797324 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5764 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13797324 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/797324
SUPPLEMENTING WIRE BONDS Mar 11, 2013 Abandoned
Array ( [id] => 8950694 [patent_doc_number] => 20130196475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'Transistor with Etching Stop Layer and Manufacturing Method Thereof' [patent_app_type] => utility [patent_app_number] => 13/794423 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3758 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13794423 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/794423
Transistor with etching stop layer and manufacturing method thereof Mar 10, 2013 Issued
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