
Louis M Arana
Examiner (ID: 1084, Phone: (571)272-2236 , Office: P/2866 )
| Most Active Art Unit | 2866 |
| Art Unit(s) | 3621, 2862, 2831, 2613, 2215, 2859, 2866, 2858, 2605, 2618, 2607, 2857 |
| Total Applications | 2842 |
| Issued Applications | 2512 |
| Pending Applications | 102 |
| Abandoned Applications | 230 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20182134
[patent_doc_number] => 20250266092
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-21
[patent_title] => BLOCK SELECTION CIRCUIT CONTROLLING SERIES-CONNECTED PASS TRANSISTORS USING SHARED SWITCH CIRCUIT AND FLASH MEMORY INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/975798
[patent_app_country] => US
[patent_app_date] => 2024-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8359
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18975798
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/975798 | BLOCK SELECTION CIRCUIT CONTROLLING SERIES-CONNECTED PASS TRANSISTORS USING SHARED SWITCH CIRCUIT AND FLASH MEMORY INCLUDING THE SAME | Dec 9, 2024 | Pending |
Array
(
[id] => 19467657
[patent_doc_number] => 20240321327
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => PRE-DECODER CIRCUITRY
[patent_app_type] => utility
[patent_app_number] => 18/677609
[patent_app_country] => US
[patent_app_date] => 2024-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9711
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677609
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/677609 | PRE-DECODER CIRCUITRY | May 28, 2024 | Pending |
Array
(
[id] => 20229150
[patent_doc_number] => 12417804
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-16
[patent_title] => Low power management for sleep mode operation of a memory device
[patent_app_type] => utility
[patent_app_number] => 18/675997
[patent_app_country] => US
[patent_app_date] => 2024-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2408
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675997
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/675997 | Low power management for sleep mode operation of a memory device | May 27, 2024 | Issued |
Array
(
[id] => 20088542
[patent_doc_number] => 20250218478
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-03
[patent_title] => SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/669931
[patent_app_country] => US
[patent_app_date] => 2024-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9510
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 320
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18669931
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/669931 | SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME | May 20, 2024 | Pending |
Array
(
[id] => 19435730
[patent_doc_number] => 20240304228
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-12
[patent_title] => SYSTEMS AND METHODS FOR DUAL STANDBY MODES IN MEMORY
[patent_app_type] => utility
[patent_app_number] => 18/668795
[patent_app_country] => US
[patent_app_date] => 2024-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6701
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668795
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/668795 | SYSTEMS AND METHODS FOR DUAL STANDBY MODES IN MEMORY | May 19, 2024 | Pending |
Array
(
[id] => 19917457
[patent_doc_number] => 12292826
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-06
[patent_title] => Method for managing a memory apparatus
[patent_app_type] => utility
[patent_app_number] => 18/663114
[patent_app_country] => US
[patent_app_date] => 2024-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 9173
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663114
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/663114 | Method for managing a memory apparatus | May 13, 2024 | Issued |
Array
(
[id] => 19972226
[patent_doc_number] => 12340844
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-24
[patent_title] => Phase-change memory cell and method for fabricating the same
[patent_app_type] => utility
[patent_app_number] => 18/632583
[patent_app_country] => US
[patent_app_date] => 2024-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 23
[patent_no_of_words] => 3809
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632583
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/632583 | Phase-change memory cell and method for fabricating the same | Apr 10, 2024 | Issued |
Array
(
[id] => 19500134
[patent_doc_number] => 20240339152
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-10
[patent_title] => Data Sense Amplifier Circuit with a Hybrid Architecture
[patent_app_type] => utility
[patent_app_number] => 18/627960
[patent_app_country] => US
[patent_app_date] => 2024-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10670
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18627960
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/627960 | Data Sense Amplifier Circuit with a Hybrid Architecture | Apr 4, 2024 | Pending |
Array
(
[id] => 19335362
[patent_doc_number] => 20240249792
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-25
[patent_title] => SYSTEM AND METHOD FOR EXTENDING LIFETIME OF MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/625895
[patent_app_country] => US
[patent_app_date] => 2024-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10017
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625895
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/625895 | SYSTEM AND METHOD FOR EXTENDING LIFETIME OF MEMORY DEVICE | Apr 2, 2024 | Pending |
Array
(
[id] => 19531488
[patent_doc_number] => 20240355390
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => STORAGE SYSTEM FOR PROCESSING GENOME SEQUENCES
[patent_app_type] => utility
[patent_app_number] => 18/595672
[patent_app_country] => US
[patent_app_date] => 2024-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5530
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18595672
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/595672 | STORAGE SYSTEM FOR PROCESSING GENOME SEQUENCES | Mar 4, 2024 | Pending |
Array
(
[id] => 19893050
[patent_doc_number] => 20250118362
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-10
[patent_title] => BANKED SENSE AMPLIFIER CIRCUIT FOR A MEMORY CORE AND A MEMORY CORE COMPLEX
[patent_app_type] => utility
[patent_app_number] => 18/581069
[patent_app_country] => US
[patent_app_date] => 2024-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4931
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581069
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/581069 | BANKED SENSE AMPLIFIER CIRCUIT FOR A MEMORY CORE AND A MEMORY CORE COMPLEX | Feb 18, 2024 | Pending |
Array
(
[id] => 20375087
[patent_doc_number] => 12482529
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-25
[patent_title] => Memory with built-in synchronous-write-through redundancy and associated test method
[patent_app_type] => utility
[patent_app_number] => 18/443347
[patent_app_country] => US
[patent_app_date] => 2024-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 0
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443347
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/443347 | Memory with built-in synchronous-write-through redundancy and associated test method | Feb 15, 2024 | Issued |
Array
(
[id] => 19192255
[patent_doc_number] => 20240171168
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-23
[patent_title] => DELAY CALIBRATION CIRCUIT, MEMORY, AND CLOCK SIGNAL CALIBRATION METHOD
[patent_app_type] => utility
[patent_app_number] => 18/428328
[patent_app_country] => US
[patent_app_date] => 2024-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10120
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428328
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/428328 | DELAY CALIBRATION CIRCUIT, MEMORY, AND CLOCK SIGNAL CALIBRATION METHOD | Jan 30, 2024 | Pending |
Array
(
[id] => 19348886
[patent_doc_number] => 20240257850
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-01
[patent_title] => MEMORY SYSTEM, OPERATING METHOD OF THE MEMORY SYSTEM, AND INTERFACE CIRCUIT OF THE MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/426825
[patent_app_country] => US
[patent_app_date] => 2024-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9038
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426825
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/426825 | MEMORY SYSTEM, OPERATING METHOD OF THE MEMORY SYSTEM, AND INTERFACE CIRCUIT OF THE MEMORY SYSTEM | Jan 29, 2024 | Pending |
Array
(
[id] => 19335352
[patent_doc_number] => 20240249782
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-25
[patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/423047
[patent_app_country] => US
[patent_app_date] => 2024-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15179
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423047
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/423047 | MEMORY SYSTEM AND OPERATING METHOD THEREOF | Jan 24, 2024 | Pending |
Array
(
[id] => 19712357
[patent_doc_number] => 20250022499
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-16
[patent_title] => MEMORY SYSTEM AND OPERATING METHOD
[patent_app_type] => utility
[patent_app_number] => 18/403739
[patent_app_country] => US
[patent_app_date] => 2024-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8602
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403739
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/403739 | MEMORY SYSTEM AND OPERATING METHOD | Jan 3, 2024 | Pending |
Array
(
[id] => 19160856
[patent_doc_number] => 20240153563
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-09
[patent_title] => SEMICONDUCTOR MEMORY DEVICE AND STORAGE SYSTEM INCLUDING SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/545144
[patent_app_country] => US
[patent_app_date] => 2023-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14319
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 298
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18545144
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/545144 | Semiconductor memory device and storage system including semiconductor memory device | Dec 18, 2023 | Issued |
Array
(
[id] => 19788253
[patent_doc_number] => 20250061932
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-20
[patent_title] => ELECTRONIC DEVICE AND ELECTRONIC SYSTEM FOR PERFORMING PHASE ADJUSTMENT OPERATION
[patent_app_type] => utility
[patent_app_number] => 18/541678
[patent_app_country] => US
[patent_app_date] => 2023-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15416
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18541678
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/541678 | ELECTRONIC DEVICE AND ELECTRONIC SYSTEM FOR PERFORMING PHASE ADJUSTMENT OPERATION | Dec 14, 2023 | Pending |
Array
(
[id] => 19100784
[patent_doc_number] => 20240120012
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-11
[patent_title] => MULTI-SAMPLED, CHARGE-SHARING THERMOMETER IN MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/539798
[patent_app_country] => US
[patent_app_date] => 2023-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9272
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18539798
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/539798 | Multi-sampled, charge-sharing thermometer in memory device | Dec 13, 2023 | Issued |
Array
(
[id] => 19348920
[patent_doc_number] => 20240257884
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-01
[patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/538457
[patent_app_country] => US
[patent_app_date] => 2023-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7850
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 16
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538457
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/538457 | SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR MEMORY DEVICE | Dec 12, 2023 | Pending |