Luan Joy Sherman

Array ( [id] => 1014590 [patent_doc_number] => 06893932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-17 [patent_title] => 'Heterojunction bipolar transistor containing at least one silicon carbide layer' [patent_app_type] => utility [patent_app_number] => 10/826120 [patent_app_country] => US [patent_app_date] => 2004-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2773 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/893/06893932.pdf [firstpage_image] =>[orig_patent_app_number] => 10826120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7375389 [patent_doc_number] => 20040178446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Method of forming asymmetrical polysilicon thin film transistor' [patent_app_type] => new [patent_app_number] => 10/811729 [patent_app_country] => US [patent_app_date] => 2004-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1759 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20040178446.pdf [firstpage_image] =>[orig_patent_app_number] => 10811729 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1068719 [patent_doc_number] => 06844245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-18 [patent_title] => 'Method of preparing a self-passivating Cu laser fuse' [patent_app_type] => utility [patent_app_number] => 10/745263 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2095 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/844/06844245.pdf [firstpage_image] =>[orig_patent_app_number] => 10745263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1047374 [patent_doc_number] => 06864561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-08 [patent_title] => 'Method and apparatus for reducing fixed charge in semiconductor device layers' [patent_app_type] => utility [patent_app_number] => 10/727889 [patent_app_country] => US [patent_app_date] => 2003-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2224 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/864/06864561.pdf [firstpage_image] =>[orig_patent_app_number] => 10727889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7466835 [patent_doc_number] => 20040102016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Method for forming an isolation region in a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/682031 [patent_app_country] => US [patent_app_date] => 2003-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2428 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20040102016.pdf [firstpage_image] =>[orig_patent_app_number] => 10682031 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 999852 [patent_doc_number] => 06911703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-28 [patent_title] => 'Semiconductor integrated circuit device operating with low power consumption' [patent_app_type] => utility [patent_app_number] => 10/680397 [patent_app_country] => US [patent_app_date] => 2003-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 135 [patent_no_of_words] => 55373 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/911/06911703.pdf [firstpage_image] =>[orig_patent_app_number] => 10680397 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 991070 [patent_doc_number] => 06919597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-19 [patent_title] => 'Bismuth titanium silicon oxide, bismuth titanium silicon oxide thin film, and method for forming the thin film' [patent_app_type] => utility [patent_app_number] => 10/634841 [patent_app_country] => US [patent_app_date] => 2003-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 7407 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/919/06919597.pdf [firstpage_image] =>[orig_patent_app_number] => 10634841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7120351 [patent_doc_number] => 20050012180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'BIPOLAR TRANSISTOR SELF-ALIGNMENT WITH RAISED EXTRINSIC BASE EXTENSION AND METHODS OF FORMING SAME' [patent_app_type] => utility [patent_app_number] => 10/604212 [patent_app_country] => US [patent_app_date] => 2003-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4930 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20050012180.pdf [firstpage_image] =>[orig_patent_app_number] => 10604212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 972137 [patent_doc_number] => 06936522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-30 [patent_title] => 'Selective silicon-on-insulator isolation structure and method' [patent_app_type] => utility [patent_app_number] => 10/604102 [patent_app_country] => US [patent_app_date] => 2003-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 31 [patent_no_of_words] => 4825 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/936/06936522.pdf [firstpage_image] =>[orig_patent_app_number] => 10604102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6662183 [patent_doc_number] => 20030201509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Pinned floating photoreceptor with active pixel sensor' [patent_app_type] => new [patent_app_number] => 10/443839 [patent_app_country] => US [patent_app_date] => 2003-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1643 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20030201509.pdf [firstpage_image] =>[orig_patent_app_number] => 10443839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7448110 [patent_doc_number] => 20040164354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Minimum-dimension,\n fully- silicided MOS driver and ESD protection design for optimized inter-finger coupling' [patent_app_type] => new [patent_app_number] => 10/435817 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6741 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20040164354.pdf [firstpage_image] =>[orig_patent_app_number] => 10435817 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7291791 [patent_doc_number] => 20040212048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Semiconductor structures, and methods of forming rugged semiconductor-containing surfaces' [patent_app_type] => new [patent_app_number] => 10/423111 [patent_app_country] => US [patent_app_date] => 2003-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6489 [patent_no_of_claims] => 84 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20040212048.pdf [firstpage_image] =>[orig_patent_app_number] => 10423111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 972656 [patent_doc_number] => 06936905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-30 [patent_title] => 'Two mask shottky diode with locos structure' [patent_app_type] => utility [patent_app_number] => 10/421781 [patent_app_country] => US [patent_app_date] => 2003-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2181 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/936/06936905.pdf [firstpage_image] =>[orig_patent_app_number] => 10421781 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7612455 [patent_doc_number] => 06903381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Light-emitting diode with cavity containing a filler' [patent_app_type] => utility [patent_app_number] => 10/421742 [patent_app_country] => US [patent_app_date] => 2003-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2885 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/903/06903381.pdf [firstpage_image] =>[orig_patent_app_number] => 10421742 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7447667 [patent_doc_number] => 20040164313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Trench capacitor with buried strap' [patent_app_type] => new [patent_app_number] => 10/248801 [patent_app_country] => US [patent_app_date] => 2003-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4064 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20040164313.pdf [firstpage_image] =>[orig_patent_app_number] => 10248801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1015023 [patent_doc_number] => 06894367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-17 [patent_title] => 'Vertical bipolar transistor' [patent_app_type] => utility [patent_app_number] => 10/367005 [patent_app_country] => US [patent_app_date] => 2003-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2905 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/894/06894367.pdf [firstpage_image] =>[orig_patent_app_number] => 10367005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1024529 [patent_doc_number] => 06884674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-26 [patent_title] => 'Method for fabricating a semiconductor device including a capacitance insulating film having a perovskite structure' [patent_app_type] => utility [patent_app_number] => 10/365502 [patent_app_country] => US [patent_app_date] => 2003-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 5616 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/884/06884674.pdf [firstpage_image] =>[orig_patent_app_number] => 10365502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1120845 [patent_doc_number] => 06798020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'High-voltage lateral transistor with a multi-layered extended drain structure' [patent_app_type] => B2 [patent_app_number] => 10/361377 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 6353 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/798/06798020.pdf [firstpage_image] =>[orig_patent_app_number] => 10361377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1080471 [patent_doc_number] => 06835629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-28 [patent_title] => 'Power integrated circuit with vertical current flow and related manufacturing process' [patent_app_type] => B2 [patent_app_number] => 10/350403 [patent_app_country] => US [patent_app_date] => 2003-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 4521 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/835/06835629.pdf [firstpage_image] =>[orig_patent_app_number] => 10350403 [rel_patent_id] =>[rel_patent_doc_number] =>)