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Luan Joy Sherman

Examiner (ID: 14942)

Most Active Art Unit
2936
Art Unit(s)
2936
Total Applications
6
Issued Applications
6
Pending Applications
0
Abandoned Applications
0

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4410634 [patent_doc_number] => 06271558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Capacitors and capacitor construction' [patent_app_type] => 1 [patent_app_number] => 9/105770 [patent_app_country] => US [patent_app_date] => 1998-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1704 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271558.pdf [firstpage_image] =>[orig_patent_app_number] => 105770 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/105770
Capacitors and capacitor construction Jun 25, 1998 Issued
Array ( [id] => 4389872 [patent_doc_number] => 06262462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Enhanced dielectric constant gate insulator' [patent_app_type] => 1 [patent_app_number] => 9/102191 [patent_app_country] => US [patent_app_date] => 1998-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1757 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/262/06262462.pdf [firstpage_image] =>[orig_patent_app_number] => 102191 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/102191
Enhanced dielectric constant gate insulator Jun 21, 1998 Issued
Array ( [id] => 1580404 [patent_doc_number] => 06448647 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'BGA package substrate' [patent_app_type] => B1 [patent_app_number] => 09/090633 [patent_app_country] => US [patent_app_date] => 1998-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 3201 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448647.pdf [firstpage_image] =>[orig_patent_app_number] => 09090633 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/090633
BGA package substrate Jun 3, 1998 Issued
Array ( [id] => 4123299 [patent_doc_number] => 06072205 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Passive element circuit' [patent_app_type] => 1 [patent_app_number] => 9/090533 [patent_app_country] => US [patent_app_date] => 1998-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2459 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072205.pdf [firstpage_image] =>[orig_patent_app_number] => 090533 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/090533
Passive element circuit Jun 3, 1998 Issued
Array ( [id] => 4090737 [patent_doc_number] => 06025627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Alternate method and structure for improved floating gate tunneling devices' [patent_app_type] => 1 [patent_app_number] => 9/087473 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5718 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025627.pdf [firstpage_image] =>[orig_patent_app_number] => 087473 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/087473
Alternate method and structure for improved floating gate tunneling devices May 28, 1998 Issued
Array ( [id] => 4197588 [patent_doc_number] => 06043543 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Read-only memory cell configuration with trench MOS transistor and widened drain region' [patent_app_type] => 1 [patent_app_number] => 9/086011 [patent_app_country] => US [patent_app_date] => 1998-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 4805 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/043/06043543.pdf [firstpage_image] =>[orig_patent_app_number] => 086011 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/086011
Read-only memory cell configuration with trench MOS transistor and widened drain region May 27, 1998 Issued
Array ( [id] => 4102278 [patent_doc_number] => 06097103 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Semiconductor device having an improved interconnection and method for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/081283 [patent_app_country] => US [patent_app_date] => 1998-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 34 [patent_no_of_words] => 11661 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097103.pdf [firstpage_image] =>[orig_patent_app_number] => 081283 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/081283
Semiconductor device having an improved interconnection and method for fabricating the same May 19, 1998 Issued
Array ( [id] => 1399179 [patent_doc_number] => 06545297 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'High density vertical SRAM cell using bipolar latchup induced by gated diode breakdown' [patent_app_type] => B1 [patent_app_number] => 09/076487 [patent_app_country] => US [patent_app_date] => 1998-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 4200 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/545/06545297.pdf [firstpage_image] =>[orig_patent_app_number] => 09076487 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/076487
High density vertical SRAM cell using bipolar latchup induced by gated diode breakdown May 12, 1998 Issued
Array ( [id] => 4355802 [patent_doc_number] => 06215190 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Borderless contact to diffusion with respect to gate conductor and methods for fabricating' [patent_app_type] => 1 [patent_app_number] => 9/076525 [patent_app_country] => US [patent_app_date] => 1998-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 5353 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215190.pdf [firstpage_image] =>[orig_patent_app_number] => 076525 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/076525
Borderless contact to diffusion with respect to gate conductor and methods for fabricating May 11, 1998 Issued
Array ( [id] => 4222342 [patent_doc_number] => 06111293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Silicon-on-insulator MOS structure' [patent_app_type] => 1 [patent_app_number] => 9/076362 [patent_app_country] => US [patent_app_date] => 1998-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2220 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/111/06111293.pdf [firstpage_image] =>[orig_patent_app_number] => 076362 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/076362
Silicon-on-insulator MOS structure May 10, 1998 Issued
Array ( [id] => 4137215 [patent_doc_number] => 06034417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Semiconductor structure having more usable substrate area and method for forming same' [patent_app_type] => 1 [patent_app_number] => 9/075391 [patent_app_country] => US [patent_app_date] => 1998-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3069 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034417.pdf [firstpage_image] =>[orig_patent_app_number] => 075391 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/075391
Semiconductor structure having more usable substrate area and method for forming same May 7, 1998 Issued
Array ( [id] => 4101866 [patent_doc_number] => 06097077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Programmable interconnect structures and programmable integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/075493 [patent_app_country] => US [patent_app_date] => 1998-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8161 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097077.pdf [firstpage_image] =>[orig_patent_app_number] => 075493 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/075493
Programmable interconnect structures and programmable integrated circuits May 7, 1998 Issued
Array ( [id] => 4038520 [patent_doc_number] => 05942777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Memory device including a memory array having a combination of trench capacitor DRAM cells and stacked capacitor DRAM cells' [patent_app_type] => 1 [patent_app_number] => 9/073039 [patent_app_country] => US [patent_app_date] => 1998-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3333 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/942/05942777.pdf [firstpage_image] =>[orig_patent_app_number] => 073039 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/073039
Memory device including a memory array having a combination of trench capacitor DRAM cells and stacked capacitor DRAM cells May 4, 1998 Issued
Array ( [id] => 4299743 [patent_doc_number] => 06180973 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Semiconductor memory device and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/069853 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 62 [patent_no_of_words] => 8946 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 367 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180973.pdf [firstpage_image] =>[orig_patent_app_number] => 069853 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/069853
Semiconductor memory device and method for manufacturing the same Apr 29, 1998 Issued
Array ( [id] => 4105082 [patent_doc_number] => 06066875 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Method of fabricating split-gate source side injection flash EEPROM array' [patent_app_type] => 1 [patent_app_number] => 9/063032 [patent_app_country] => US [patent_app_date] => 1998-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2864 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/066/06066875.pdf [firstpage_image] =>[orig_patent_app_number] => 063032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063032
Method of fabricating split-gate source side injection flash EEPROM array Apr 19, 1998 Issued
Array ( [id] => 4197399 [patent_doc_number] => 06043530 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Flash EEPROM device employing polysilicon sidewall spacer as an erase gate' [patent_app_type] => 1 [patent_app_number] => 9/060673 [patent_app_country] => US [patent_app_date] => 1998-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 4889 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/043/06043530.pdf [firstpage_image] =>[orig_patent_app_number] => 060673 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/060673
Flash EEPROM device employing polysilicon sidewall spacer as an erase gate Apr 14, 1998 Issued
Array ( [id] => 4075897 [patent_doc_number] => 06069385 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Trench MOS-gated device' [patent_app_type] => 1 [patent_app_number] => 9/057913 [patent_app_country] => US [patent_app_date] => 1998-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 4589 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069385.pdf [firstpage_image] =>[orig_patent_app_number] => 057913 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/057913
Trench MOS-gated device Apr 8, 1998 Issued
Array ( [id] => 4189389 [patent_doc_number] => 06150696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Semiconductor substrate and method of fabricating semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/055903 [patent_app_country] => US [patent_app_date] => 1998-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 46 [patent_no_of_words] => 11333 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150696.pdf [firstpage_image] =>[orig_patent_app_number] => 055903 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/055903
Semiconductor substrate and method of fabricating semiconductor device Apr 6, 1998 Issued
09/053041 THIN FILM SEMICONDUCTOR DEVICE UNIFORMING CHARACTERISTICS OF SEMICONDUCTOR ELEMENTS AND MANUFACTURING METHOD THEREOF Mar 31, 1998 Abandoned
Array ( [id] => 1428118 [patent_doc_number] => 06504211 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Circuit for device isolation' [patent_app_type] => B1 [patent_app_number] => 09/053352 [patent_app_country] => US [patent_app_date] => 1998-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3232 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/504/06504211.pdf [firstpage_image] =>[orig_patent_app_number] => 09053352 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/053352
Circuit for device isolation Mar 31, 1998 Issued
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