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Luan Joy Sherman

Examiner (ID: 14942)

Most Active Art Unit
2936
Art Unit(s)
2936
Total Applications
6
Issued Applications
6
Pending Applications
0
Abandoned Applications
0

Applications

Application numberTitle of the applicationFiling DateStatus
09/635532 SEMICONDUCTOR DEVICE HAVING SINGLE SILICON OXIDE NITRIDE GATE INSULATING LAYER Aug 8, 2000 Abandoned
Array ( [id] => 1468515 [patent_doc_number] => 06459121 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Method for producing non-violatile semiconductor memory device and the device' [patent_app_type] => B1 [patent_app_number] => 09/621533 [patent_app_country] => US [patent_app_date] => 2000-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 52 [patent_no_of_words] => 9812 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/459/06459121.pdf [firstpage_image] =>[orig_patent_app_number] => 09621533 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/621533
Method for producing non-violatile semiconductor memory device and the device Jul 20, 2000 Issued
Array ( [id] => 1544327 [patent_doc_number] => 06373123 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Semiconductor structure having more usable substrate area and method for forming same' [patent_app_type] => B1 [patent_app_number] => 09/613107 [patent_app_country] => US [patent_app_date] => 2000-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3154 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373123.pdf [firstpage_image] =>[orig_patent_app_number] => 09613107 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/613107
Semiconductor structure having more usable substrate area and method for forming same Jul 9, 2000 Issued
Array ( [id] => 1428098 [patent_doc_number] => 06504207 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the same' [patent_app_type] => B1 [patent_app_number] => 09/609292 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 3879 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/504/06504207.pdf [firstpage_image] =>[orig_patent_app_number] => 09609292 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/609292
Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the same Jun 29, 2000 Issued
Array ( [id] => 1018658 [patent_doc_number] => 06891237 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-10 [patent_title] => 'Organic semiconductor device having an active dielectric layer comprising silsesquioxanes' [patent_app_type] => utility [patent_app_number] => 09/603941 [patent_app_country] => US [patent_app_date] => 2000-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 6753 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/891/06891237.pdf [firstpage_image] =>[orig_patent_app_number] => 09603941 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/603941
Organic semiconductor device having an active dielectric layer comprising silsesquioxanes Jun 26, 2000 Issued
Array ( [id] => 1404717 [patent_doc_number] => 06531777 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Barrier metal integrity testing using a dual level line to line leakage testing pattern and partial CMP' [patent_app_type] => B1 [patent_app_number] => 09/599839 [patent_app_country] => US [patent_app_date] => 2000-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 431 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/531/06531777.pdf [firstpage_image] =>[orig_patent_app_number] => 09599839 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/599839
Barrier metal integrity testing using a dual level line to line leakage testing pattern and partial CMP Jun 21, 2000 Issued
Array ( [id] => 1309832 [patent_doc_number] => 06617621 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'Gate array architecture using elevated metal levels for customization' [patent_app_type] => B1 [patent_app_number] => 09/588802 [patent_app_country] => US [patent_app_date] => 2000-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 9500 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/617/06617621.pdf [firstpage_image] =>[orig_patent_app_number] => 09588802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/588802
Gate array architecture using elevated metal levels for customization Jun 5, 2000 Issued
Array ( [id] => 1509317 [patent_doc_number] => 06441430 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Semiconductor device with floating gates' [patent_app_type] => B1 [patent_app_number] => 09/588761 [patent_app_country] => US [patent_app_date] => 2000-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 185 [patent_no_of_words] => 12974 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/441/06441430.pdf [firstpage_image] =>[orig_patent_app_number] => 09588761 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/588761
Semiconductor device with floating gates Jun 5, 2000 Issued
Array ( [id] => 1463649 [patent_doc_number] => 06351005 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Integrated capacitor incorporating high K dielectric' [patent_app_type] => B1 [patent_app_number] => 09/579821 [patent_app_country] => US [patent_app_date] => 2000-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5310 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351005.pdf [firstpage_image] =>[orig_patent_app_number] => 09579821 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/579821
Integrated capacitor incorporating high K dielectric May 24, 2000 Issued
Array ( [id] => 1554648 [patent_doc_number] => 06348713 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/577717 [patent_app_country] => US [patent_app_date] => 2000-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3056 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348713.pdf [firstpage_image] =>[orig_patent_app_number] => 09577717 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/577717
Method for fabricating semiconductor device May 22, 2000 Issued
Array ( [id] => 1293425 [patent_doc_number] => 06630721 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Polysilicon sidewall with silicide formation to produce high performance MOSFETS' [patent_app_type] => B1 [patent_app_number] => 09/571823 [patent_app_country] => US [patent_app_date] => 2000-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 7776 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/630/06630721.pdf [firstpage_image] =>[orig_patent_app_number] => 09571823 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/571823
Polysilicon sidewall with silicide formation to produce high performance MOSFETS May 15, 2000 Issued
Array ( [id] => 1536487 [patent_doc_number] => 06489662 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Semiconductor integrated circuit device formed on SOI substrate' [patent_app_type] => B1 [patent_app_number] => 09/559373 [patent_app_country] => US [patent_app_date] => 2000-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 6577 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/489/06489662.pdf [firstpage_image] =>[orig_patent_app_number] => 09559373 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/559373
Semiconductor integrated circuit device formed on SOI substrate Apr 26, 2000 Issued
Array ( [id] => 1336548 [patent_doc_number] => 06597033 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Semiconductor memory device and manufacturing method thereof' [patent_app_type] => B1 [patent_app_number] => 09/552583 [patent_app_country] => US [patent_app_date] => 2000-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6349 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/597/06597033.pdf [firstpage_image] =>[orig_patent_app_number] => 09552583 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/552583
Semiconductor memory device and manufacturing method thereof Apr 18, 2000 Issued
Array ( [id] => 1461449 [patent_doc_number] => 06392274 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'High-voltage metal-oxide-semiconductor transistor' [patent_app_type] => B1 [patent_app_number] => 09/542842 [patent_app_country] => US [patent_app_date] => 2000-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2842 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392274.pdf [firstpage_image] =>[orig_patent_app_number] => 09542842 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/542842
High-voltage metal-oxide-semiconductor transistor Apr 3, 2000 Issued
Array ( [id] => 1384407 [patent_doc_number] => 06559505 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Power integrated circuit with vertical current flow and related manufacturing process' [patent_app_type] => B1 [patent_app_number] => 09/542092 [patent_app_country] => US [patent_app_date] => 2000-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 4474 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559505.pdf [firstpage_image] =>[orig_patent_app_number] => 09542092 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/542092
Power integrated circuit with vertical current flow and related manufacturing process Apr 2, 2000 Issued
09/536751 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING INSULATOR FILM FORMED FROM A LIQUID CONTAINING A POLYMER OF SILCON, OXYGEN AND HYDROGEN Mar 27, 2000 Abandoned
Array ( [id] => 1480535 [patent_doc_number] => 06452233 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'SOI device having a leakage stopping layer' [patent_app_type] => B1 [patent_app_number] => 09/531893 [patent_app_country] => US [patent_app_date] => 2000-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6358 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/452/06452233.pdf [firstpage_image] =>[orig_patent_app_number] => 09531893 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531893
SOI device having a leakage stopping layer Mar 20, 2000 Issued
Array ( [id] => 1420661 [patent_doc_number] => 06521943 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Semiconductor device having thin electrode layer adjacent gate insulator and method of manufacture' [patent_app_type] => B1 [patent_app_number] => 09/520346 [patent_app_country] => US [patent_app_date] => 2000-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 29 [patent_no_of_words] => 14180 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/521/06521943.pdf [firstpage_image] =>[orig_patent_app_number] => 09520346 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/520346
Semiconductor device having thin electrode layer adjacent gate insulator and method of manufacture Mar 6, 2000 Issued
Array ( [id] => 1497047 [patent_doc_number] => 06404024 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/517051 [patent_app_country] => US [patent_app_date] => 2000-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 28 [patent_no_of_words] => 10922 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404024.pdf [firstpage_image] =>[orig_patent_app_number] => 09517051 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/517051
Semiconductor device Mar 1, 2000 Issued
09/516073 Complementary integrated circuit and method of manufacturing same Feb 29, 2000 Abandoned
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