Luan Joy Sherman

Array ( [id] => 1496986 [patent_doc_number] => 06404009 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Semiconductor device and method of producing the same' [patent_app_type] => B1 [patent_app_number] => 09/514591 [patent_app_country] => US [patent_app_date] => 2000-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4309 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404009.pdf [firstpage_image] =>[orig_patent_app_number] => 09514591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1580254 [patent_doc_number] => 06448606 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Semiconductor with increased gate coupling coefficient' [patent_app_type] => B1 [patent_app_number] => 09/513261 [patent_app_country] => US [patent_app_date] => 2000-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 4523 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448606.pdf [firstpage_image] =>[orig_patent_app_number] => 09513261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1568378 [patent_doc_number] => 06376877 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Double self-aligning shallow trench isolation semiconductor and manufacturing method therefor' [patent_app_type] => B1 [patent_app_number] => 09/513260 [patent_app_country] => US [patent_app_date] => 2000-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 3548 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376877.pdf [firstpage_image] =>[orig_patent_app_number] => 09513260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1502305 [patent_doc_number] => 06486524 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Ultra low Irr fast recovery diode' [patent_app_type] => B1 [patent_app_number] => 09/510752 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3357 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486524.pdf [firstpage_image] =>[orig_patent_app_number] => 09510752 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1419293 [patent_doc_number] => 06525389 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'High voltage termination with amorphous silicon layer below the field plate' [patent_app_type] => B1 [patent_app_number] => 09/510613 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3352 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525389.pdf [firstpage_image] =>[orig_patent_app_number] => 09510613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1314351 [patent_doc_number] => 06614088 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Breakdown improvement method and sturcture for lateral DMOS device' [patent_app_type] => B1 [patent_app_number] => 09/506711 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2719 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/614/06614088.pdf [firstpage_image] =>[orig_patent_app_number] => 09506711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4387297 [patent_doc_number] => 06294813 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Information handling system having improved floating gate tunneling devices' [patent_app_type] => 1 [patent_app_number] => 9/504496 [patent_app_country] => US [patent_app_date] => 2000-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5718 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294813.pdf [firstpage_image] =>[orig_patent_app_number] => 504496 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1395083 [patent_doc_number] => 06548831 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Liquid crystal display panel having a gate line with at least one opening' [patent_app_type] => B1 [patent_app_number] => 09/502453 [patent_app_country] => US [patent_app_date] => 2000-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 4733 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548831.pdf [firstpage_image] =>[orig_patent_app_number] => 09502453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1471621 [patent_doc_number] => 06407435 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Multilayer dielectric stack and method' [patent_app_type] => B1 [patent_app_number] => 09/502420 [patent_app_country] => US [patent_app_date] => 2000-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3848 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/407/06407435.pdf [firstpage_image] =>[orig_patent_app_number] => 09502420 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1340245 [patent_doc_number] => 06593592 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Semiconductor device having thin film transistors' [patent_app_type] => B1 [patent_app_number] => 09/493411 [patent_app_country] => US [patent_app_date] => 2000-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 50 [patent_no_of_words] => 18816 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593592.pdf [firstpage_image] =>[orig_patent_app_number] => 09493411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1406655 [patent_doc_number] => 06538290 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Static protection device' [patent_app_type] => B1 [patent_app_number] => 09/492072 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 1953 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/538/06538290.pdf [firstpage_image] =>[orig_patent_app_number] => 09492072 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1576342 [patent_doc_number] => 06469360 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Integrated circuit devices providing reduced electric fields during fabrication thereof' [patent_app_type] => B1 [patent_app_number] => 09/481030 [patent_app_country] => US [patent_app_date] => 2000-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2147 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469360.pdf [firstpage_image] =>[orig_patent_app_number] => 09481030 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1384302 [patent_doc_number] => 06559499 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Process for fabricating an integrated circuit device having capacitors with a multilevel metallization' [patent_app_type] => B1 [patent_app_number] => 09/477310 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3748 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559499.pdf [firstpage_image] =>[orig_patent_app_number] => 09477310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4350936 [patent_doc_number] => 06285060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Barrier accumulation-mode MOSFET' [patent_app_type] => 1 [patent_app_number] => 9/476320 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 7431 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285060.pdf [firstpage_image] =>[orig_patent_app_number] => 476320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1554624 [patent_doc_number] => 06348705 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Low temperature process for high density thin film integrated capacitors and amorphously frustrated ferroelectric materials therefor' [patent_app_type] => B1 [patent_app_number] => 09/469700 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 11129 [patent_no_of_claims] => 78 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348705.pdf [firstpage_image] =>[orig_patent_app_number] => 09469700 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4336666 [patent_doc_number] => 06313500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Split gate memory cell' [patent_app_type] => 1 [patent_app_number] => 9/460812 [patent_app_country] => US [patent_app_date] => 1999-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2355 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/313/06313500.pdf [firstpage_image] =>[orig_patent_app_number] => 460812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1210886 [patent_doc_number] => 06713824 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Reliable semiconductor device and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/459913 [patent_app_country] => US [patent_app_date] => 1999-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 5084 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713824.pdf [firstpage_image] =>[orig_patent_app_number] => 09459913 [rel_patent_id] =>[rel_patent_doc_number] =>)