Search

Luan Kim Bui

Examiner (ID: 2622, Phone: (571)272-4552 , Office: P/3728 )

Most Active Art Unit
3728
Art Unit(s)
3736, 3728, 2899, 3208, 3727
Total Applications
3674
Issued Applications
2546
Pending Applications
236
Abandoned Applications
892

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17063351 [patent_doc_number] => 11107966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => Two-sided Majorana fermion quantum computing devices fabricated with ion implant methods [patent_app_type] => utility [patent_app_number] => 16/680117 [patent_app_country] => US [patent_app_date] => 2019-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 11648 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16680117 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/680117
Two-sided Majorana fermion quantum computing devices fabricated with ion implant methods Nov 10, 2019 Issued
Array ( [id] => 17284091 [patent_doc_number] => 11201133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Bonding apparatus and method [patent_app_type] => utility [patent_app_number] => 16/675039 [patent_app_country] => US [patent_app_date] => 2019-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 8065 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16675039 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/675039
Bonding apparatus and method Nov 4, 2019 Issued
Array ( [id] => 15503497 [patent_doc_number] => 20200051937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => LOW TEMPERATURE BONDED STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/655002 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9183 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16655002 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/655002
Low temperature bonded structures Oct 15, 2019 Issued
Array ( [id] => 17456199 [patent_doc_number] => 11271066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Flexible array substrate with stress cushion part and display device having the same [patent_app_type] => utility [patent_app_number] => 16/614043 [patent_app_country] => US [patent_app_date] => 2019-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4363 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16614043 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/614043
Flexible array substrate with stress cushion part and display device having the same Oct 7, 2019 Issued
Array ( [id] => 15775691 [patent_doc_number] => 20200118863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => WAFER HOLDING APPARATUS AND WAFER PROCESSING METHOD USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/595776 [patent_app_country] => US [patent_app_date] => 2019-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16595776 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/595776
Wafer holding apparatus and wafer processing method using the same Oct 7, 2019 Issued
Array ( [id] => 16293710 [patent_doc_number] => 10770566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Unique gate cap and gate cap spacer structures for devices on integrated circuit products [patent_app_type] => utility [patent_app_number] => 16/594276 [patent_app_country] => US [patent_app_date] => 2019-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 3137 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16594276 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/594276
Unique gate cap and gate cap spacer structures for devices on integrated circuit products Oct 6, 2019 Issued
Array ( [id] => 16172768 [patent_doc_number] => 10714345 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Plasma assisted doping on germanium [patent_app_type] => utility [patent_app_number] => 16/578985 [patent_app_country] => US [patent_app_date] => 2019-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4702 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16578985 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/578985
Plasma assisted doping on germanium Sep 22, 2019 Issued
Array ( [id] => 16348077 [patent_doc_number] => 20200312728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => CMOS COMPATIBLE DEVICE BASED ON FOUR-TERMINAL SWITCHING LATTICES [patent_app_type] => utility [patent_app_number] => 16/576813 [patent_app_country] => US [patent_app_date] => 2019-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16576813 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/576813
CMOS compatible device based on four-terminal switching lattices Sep 19, 2019 Issued
Array ( [id] => 17818686 [patent_doc_number] => 11424310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Display panel having adjusting layer and elastic layer and method of manufacturing the display panel [patent_app_type] => utility [patent_app_number] => 16/614298 [patent_app_country] => US [patent_app_date] => 2019-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4390 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16614298 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/614298
Display panel having adjusting layer and elastic layer and method of manufacturing the display panel Sep 18, 2019 Issued
Array ( [id] => 17048025 [patent_doc_number] => 11101215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Tapered connectors for superconductor circuits [patent_app_type] => utility [patent_app_number] => 16/575274 [patent_app_country] => US [patent_app_date] => 2019-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4230 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16575274 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/575274
Tapered connectors for superconductor circuits Sep 17, 2019 Issued
Array ( [id] => 16234089 [patent_doc_number] => 10741653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Bond-over-active circuity gallium nitride devices [patent_app_type] => utility [patent_app_number] => 16/569218 [patent_app_country] => US [patent_app_date] => 2019-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 35 [patent_no_of_words] => 4548 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16569218 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/569218
Bond-over-active circuity gallium nitride devices Sep 11, 2019 Issued
Array ( [id] => 16348109 [patent_doc_number] => 20200312760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => INTERPOSER AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/563202 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16563202 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/563202
Interposer and semiconductor package including the same Sep 5, 2019 Issued
Array ( [id] => 16865966 [patent_doc_number] => 11024719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Semiconductor device and production method thereof [patent_app_type] => utility [patent_app_number] => 16/563307 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 5555 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16563307 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/563307
Semiconductor device and production method thereof Sep 5, 2019 Issued
Array ( [id] => 16301119 [patent_doc_number] => 20200286842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/561351 [patent_app_country] => US [patent_app_date] => 2019-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8362 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16561351 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/561351
Semiconductor device including memory cell arrays and method of manufacturing the same Sep 4, 2019 Issued
Array ( [id] => 16471703 [patent_doc_number] => 20200373241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => POWER DISTRIBUTION NETWORK USING BURIED POWER RAIL [patent_app_type] => utility [patent_app_number] => 16/561340 [patent_app_country] => US [patent_app_date] => 2019-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7516 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16561340 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/561340
Power distribution network using buried power rail Sep 4, 2019 Issued
Array ( [id] => 17078062 [patent_doc_number] => 11114478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Thin film transistor and manufacture method thereof, array substrate and manufacture method thereof [patent_app_type] => utility [patent_app_number] => 16/561315 [patent_app_country] => US [patent_app_date] => 2019-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 39 [patent_no_of_words] => 14556 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16561315 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/561315
Thin film transistor and manufacture method thereof, array substrate and manufacture method thereof Sep 4, 2019 Issued
Array ( [id] => 17002464 [patent_doc_number] => 11081286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Method for manufacturing electrolytic capacitor, and electrolytic capacitor [patent_app_type] => utility [patent_app_number] => 16/562033 [patent_app_country] => US [patent_app_date] => 2019-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 10842 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16562033 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/562033
Method for manufacturing electrolytic capacitor, and electrolytic capacitor Sep 4, 2019 Issued
Array ( [id] => 16759902 [patent_doc_number] => 10978459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Semiconductor device with bit lines at different levels and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 16/561280 [patent_app_country] => US [patent_app_date] => 2019-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 93 [patent_figures_cnt] => 93 [patent_no_of_words] => 13029 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16561280 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/561280
Semiconductor device with bit lines at different levels and method for fabricating the same Sep 4, 2019 Issued
Array ( [id] => 16502412 [patent_doc_number] => 10867806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-15 [patent_title] => Semiconductor device gate structure and method of fabricating thereof [patent_app_type] => utility [patent_app_number] => 16/556531 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5363 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16556531 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/556531
Semiconductor device gate structure and method of fabricating thereof Aug 29, 2019 Issued
Array ( [id] => 15882479 [patent_doc_number] => 10647570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Fabrication process for a symmetrical MEMS accelerometer [patent_app_type] => utility [patent_app_number] => 16/552630 [patent_app_country] => US [patent_app_date] => 2019-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 45 [patent_no_of_words] => 5976 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16552630 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/552630
Fabrication process for a symmetrical MEMS accelerometer Aug 26, 2019 Issued
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