Search

Luan V. Van

Supervisory Patent Examiner (ID: 175, Phone: (571)272-8521 , Office: P/1759 )

Most Active Art Unit
1795
Art Unit(s)
1756, 1795, 1753, 1724, 1759
Total Applications
768
Issued Applications
265
Pending Applications
72
Abandoned Applications
435

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16536548 [patent_doc_number] => 10879161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Semiconductor packages having a seed layer structure protruding from an edge of metal structure [patent_app_type] => utility [patent_app_number] => 16/431751 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 10813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16431751 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/431751
Semiconductor packages having a seed layer structure protruding from an edge of metal structure Jun 4, 2019 Issued
Array ( [id] => 16637973 [patent_doc_number] => 10916488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Semiconductor package having thermal conductive pattern surrounding the semiconductor die [patent_app_type] => utility [patent_app_number] => 16/431747 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 7598 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16431747 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/431747
Semiconductor package having thermal conductive pattern surrounding the semiconductor die Jun 4, 2019 Issued
Array ( [id] => 15256997 [patent_doc_number] => 20190377232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => ACTIVE MATRIX SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/432221 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16432221 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/432221
ACTIVE MATRIX SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME Jun 4, 2019 Abandoned
Array ( [id] => 15597827 [patent_doc_number] => 20200075448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH MAGNETIC ELEMENT [patent_app_type] => utility [patent_app_number] => 16/432625 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5687 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16432625 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/432625
Structure and formation method of semiconductor device with magnetic element covered by polymer material Jun 4, 2019 Issued
Array ( [id] => 15274235 [patent_doc_number] => 20190385852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-19 [patent_title] => Semiconductor Device and Method of Manufacturing a Semiconductor Device [patent_app_type] => utility [patent_app_number] => 16/432211 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16432211 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/432211
Method of manufacturing a semiconductor device by using ion beam technique Jun 4, 2019 Issued
Array ( [id] => 15260383 [patent_doc_number] => 20190378925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/432615 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11672 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16432615 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/432615
Semiconductor device having a drain drift-region in contact with the body region Jun 4, 2019 Issued
Array ( [id] => 15462731 [patent_doc_number] => 20200044190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => METHOD FOR ENCAPSULATING DISPLAY SUBSTRATE AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/432209 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16432209 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/432209
Method for encapsulating display substrate and display device having a photo-isomerization material layer between first and second barrier walls Jun 4, 2019 Issued
Array ( [id] => 16707704 [patent_doc_number] => 10957648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Three-dimensional memory device containing contact via structure extending through source contact layer and dielectric spacer assembly [patent_app_type] => utility [patent_app_number] => 16/432415 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 53 [patent_no_of_words] => 18647 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16432415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/432415
Three-dimensional memory device containing contact via structure extending through source contact layer and dielectric spacer assembly Jun 4, 2019 Issued
Array ( [id] => 16746406 [patent_doc_number] => 10971407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Method of forming a complementary metal oxide semiconductor device having fin field effect transistors with a common metal gate [patent_app_type] => utility [patent_app_number] => 16/432346 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 7819 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16432346 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/432346
Method of forming a complementary metal oxide semiconductor device having fin field effect transistors with a common metal gate Jun 4, 2019 Issued
Array ( [id] => 14938307 [patent_doc_number] => 20190304792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => Interconnect Structure and Method of Forming the Same [patent_app_type] => utility [patent_app_number] => 16/429179 [patent_app_country] => US [patent_app_date] => 2019-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16429179 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/429179
Interconnect structure having a carbon-containing barrier layer Jun 2, 2019 Issued
Array ( [id] => 15000315 [patent_doc_number] => 20190319115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => BIPOLAR TRANSISTOR WITH TRENCH STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/427356 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5264 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16427356 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/427356
Method of manufacturing a bipolar transistor with trench structure May 30, 2019 Issued
Array ( [id] => 17319401 [patent_doc_number] => 20210408451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => ORGANIC LIGHT EMITTING DIODE AND METHOD OF FABRICATING THEREOF [patent_app_type] => utility [patent_app_number] => 16/481096 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16481096 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/481096
Organic light emitting diode comprising inverted triangular groove structure at boundary line between display region and non-display region and method of fabricating thereof May 19, 2019 Issued
Array ( [id] => 14969127 [patent_doc_number] => 20190312042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING SILICON/GERMANIUM ACTIVE REGIONS WITH DIFFERENT GERMANIUM CONCENTRATIONS [patent_app_type] => utility [patent_app_number] => 16/416477 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11752 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16416477 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/416477
Semiconductor devices having silicon/germanium active regions with different germanium concentrations May 19, 2019 Issued
Array ( [id] => 14813027 [patent_doc_number] => 20190273123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-05 [patent_title] => DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/416044 [patent_app_country] => US [patent_app_date] => 2019-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16416044 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/416044
Method of manufacturing a display device utilizing pixel and dummy portions May 16, 2019 Issued
Array ( [id] => 16593813 [patent_doc_number] => 10903090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Method of singulate a package structure using a light transmitting film on a polymer layer [patent_app_type] => utility [patent_app_number] => 16/414763 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6565 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414763 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414763
Method of singulate a package structure using a light transmitting film on a polymer layer May 15, 2019 Issued
Array ( [id] => 15370085 [patent_doc_number] => 20200020807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => FinFET Structure and Method with Reduced Fin Buckling [patent_app_type] => utility [patent_app_number] => 16/414565 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7589 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414565 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414565
Method of forming FinFET structure with reduced Fin buckling May 15, 2019 Issued
Array ( [id] => 16464351 [patent_doc_number] => 10847716 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-24 [patent_title] => Method for manufacturing a phase change memory device having a second opening above a first opening in the dielectric layer [patent_app_type] => utility [patent_app_number] => 16/414582 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 34 [patent_no_of_words] => 10915 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414582 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414582
Method for manufacturing a phase change memory device having a second opening above a first opening in the dielectric layer May 15, 2019 Issued
Array ( [id] => 17122147 [patent_doc_number] => 11133289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => Semiconductor package and manufacturing method of semiconductor package having plurality of encapsulating materials [patent_app_type] => utility [patent_app_number] => 16/414723 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 53 [patent_no_of_words] => 14676 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414723 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414723
Semiconductor package and manufacturing method of semiconductor package having plurality of encapsulating materials May 15, 2019 Issued
Array ( [id] => 16456225 [patent_doc_number] => 20200365651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => DEVICE COMPRISING SUBTRATE AND DIE WITH FRAME [patent_app_type] => utility [patent_app_number] => 16/414572 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10195 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414572 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414572
DEVICE COMPRISING SUBTRATE AND DIE WITH FRAME May 15, 2019 Abandoned
Array ( [id] => 16210603 [patent_doc_number] => 20200243593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => CMOS IMAGE SENSOR WITH COMPACT PIXEL LAYOUT [patent_app_type] => utility [patent_app_number] => 16/414669 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414669 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414669
CMOS image sensor with compact pixel layout May 15, 2019 Issued
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