Luan V. Van

Array ( [id] => 10718386 [patent_doc_number] => 20160064533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/828046 [patent_app_country] => US [patent_app_date] => 2015-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 67 [patent_figures_cnt] => 67 [patent_no_of_words] => 25720 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14828046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10718165 [patent_doc_number] => 20160064312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/827973 [patent_app_country] => US [patent_app_date] => 2015-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 26486 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14827973 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11187618 [patent_doc_number] => 09419028 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-16 [patent_title] => 'Method of manufacturing display device and forming an alignment mark having concave and convex portions formed along a first pattern' [patent_app_type] => utility [patent_app_number] => 14/827055 [patent_app_country] => US [patent_app_date] => 2015-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7785 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14827055 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11259316 [patent_doc_number] => 09484219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-01 [patent_title] => 'Methods of fabricating memory devices using wet etching and dry etching' [patent_app_type] => utility [patent_app_number] => 14/826845 [patent_app_country] => US [patent_app_date] => 2015-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 35 [patent_no_of_words] => 11504 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14826845 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11765100 [patent_doc_number] => 09373547 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-06-21 [patent_title] => 'Large-scale patterning of germanium quantum dots by stress transfer' [patent_app_type] => utility [patent_app_number] => 14/827084 [patent_app_country] => US [patent_app_date] => 2015-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 8048 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14827084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11253045 [patent_doc_number] => 09478557 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-10-25 [patent_title] => 'Process for 3D NAND memory with socketed floating gate cells' [patent_app_type] => utility [patent_app_number] => 14/825506 [patent_app_country] => US [patent_app_date] => 2015-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 176 [patent_no_of_words] => 26359 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14825506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11781778 [patent_doc_number] => 09390977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-12 [patent_title] => 'Method for manufacturing a fin=shaped field effect transistor capable of reducing a threshold voltage variation' [patent_app_type] => utility [patent_app_number] => 14/825556 [patent_app_country] => US [patent_app_date] => 2015-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 34 [patent_no_of_words] => 12618 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14825556 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11201191 [patent_doc_number] => 09431411 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-30 [patent_title] => 'Efficient process for 3D NAND memory with socketed floating gate cells' [patent_app_type] => utility [patent_app_number] => 14/825408 [patent_app_country] => US [patent_app_date] => 2015-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 176 [patent_no_of_words] => 26149 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14825408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10577306 [patent_doc_number] => 09299961 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'OLED display panel' [patent_app_type] => utility [patent_app_number] => 14/824899 [patent_app_country] => US [patent_app_date] => 2015-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4331 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14824899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11446268 [patent_doc_number] => 20170047289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'MEMORY DEVICE COMPRISING MEMORY STRINGS PENETRATING THROUGH A STACKING STRUCTURE AND ELECTRICALLY CONTACTING WITH A METAL LAYER AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/821874 [patent_app_country] => US [patent_app_date] => 2015-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3950 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14821874 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10645334 [patent_doc_number] => 09362208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components' [patent_app_type] => utility [patent_app_number] => 14/821550 [patent_app_country] => US [patent_app_date] => 2015-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4001 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14821550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11781909 [patent_doc_number] => 09391111 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-07-12 [patent_title] => 'Stacked integrated circuit system with thinned intermediate semiconductor die' [patent_app_type] => utility [patent_app_number] => 14/820992 [patent_app_country] => US [patent_app_date] => 2015-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3673 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14820992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11253025 [patent_doc_number] => 09478538 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-10-25 [patent_title] => 'Methods for forming transistor devices with different threshold voltages and the resulting devices' [patent_app_type] => utility [patent_app_number] => 14/820661 [patent_app_country] => US [patent_app_date] => 2015-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4314 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14820661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11439190 [patent_doc_number] => 20170040211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'DESMEAR WITH METALIZED PROTECTIVE FILM' [patent_app_type] => utility [patent_app_number] => 14/821647 [patent_app_country] => US [patent_app_date] => 2015-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14821647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11233729 [patent_doc_number] => 09460962 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-10-04 [patent_title] => 'Substrate contact etch process' [patent_app_type] => utility [patent_app_number] => 14/820542 [patent_app_country] => US [patent_app_date] => 2015-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3323 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14820542 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11480779 [patent_doc_number] => 09587311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Display apparatus including a thin film encapsulation layer and apparatus for and method of manufacturing the display apparatus' [patent_app_type] => utility [patent_app_number] => 14/819381 [patent_app_country] => US [patent_app_date] => 2015-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 10601 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14819381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11265949 [patent_doc_number] => 09490252 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-08 [patent_title] => 'MIM capacitor formation in RMG module' [patent_app_type] => utility [patent_app_number] => 14/819122 [patent_app_country] => US [patent_app_date] => 2015-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4061 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14819122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10455346 [patent_doc_number] => 20150340361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'SACRIFICIAL OXIDE WITH UNIFORM THICKNESS' [patent_app_type] => utility [patent_app_number] => 14/817041 [patent_app_country] => US [patent_app_date] => 2015-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6011 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14817041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11194471 [patent_doc_number] => 09425290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-23 [patent_title] => 'Formation of high quality fin in 3D structure by way of two-step implantation' [patent_app_type] => utility [patent_app_number] => 14/814591 [patent_app_country] => US [patent_app_date] => 2015-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 29 [patent_no_of_words] => 5959 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14814591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11466982 [patent_doc_number] => 09583623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Semiconductor device including fin structures disposed over buffer structures and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/815722 [patent_app_country] => US [patent_app_date] => 2015-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 29 [patent_no_of_words] => 7817 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14815722 [rel_patent_id] =>[rel_patent_doc_number] =>)