Lucien Toplu

Array ( [id] => 3473560 [patent_doc_number] => 05392426 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Method and apparatus for use in program operation, control and control block management and storage' [patent_app_type] => 1 [patent_app_number] => 8/006688 [patent_app_country] => US [patent_app_date] => 1993-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 5213 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392426.pdf [firstpage_image] =>[orig_patent_app_number] => 006688 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3670566 [patent_doc_number] => 05659751 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Apparatus and method for dynamic linking of computer software components' [patent_app_type] => 1 [patent_app_number] => 7/985449 [patent_app_country] => US [patent_app_date] => 1992-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5997 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659751.pdf [firstpage_image] =>[orig_patent_app_number] => 985449 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3049602 [patent_doc_number] => 05301279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Apparatus for conditioning priority arbitration' [patent_app_type] => 1 [patent_app_number] => 7/982133 [patent_app_country] => US [patent_app_date] => 1992-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7676 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/301/05301279.pdf [firstpage_image] =>[orig_patent_app_number] => 982133 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3580002 [patent_doc_number] => 05485626 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Architectural enhancements for parallel computer systems utilizing encapsulation of queuing allowing small grain processing' [patent_app_type] => 1 [patent_app_number] => 7/970729 [patent_app_country] => US [patent_app_date] => 1992-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 21484 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/485/05485626.pdf [firstpage_image] =>[orig_patent_app_number] => 970729 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3035673 [patent_doc_number] => 05289585 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-22 [patent_title] => 'Multiprocessor system having a system bus for the coupling of several processing units with appertaining private cache memories and a common main memory' [patent_app_type] => 1 [patent_app_number] => 7/917684 [patent_app_country] => US [patent_app_date] => 1992-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6111 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 474 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/289/05289585.pdf [firstpage_image] =>[orig_patent_app_number] => 917684 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3133075 [patent_doc_number] => 05450572 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-12 [patent_title] => 'Quasi-synchronous information transfer and phase alignment means for enabling same' [patent_app_type] => 1 [patent_app_number] => 7/916319 [patent_app_country] => US [patent_app_date] => 1992-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4583 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/450/05450572.pdf [firstpage_image] =>[orig_patent_app_number] => 916319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3537528 [patent_doc_number] => 05504894 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-02 [patent_title] => 'Workload manager for achieving transaction class response time goals in a multiprocessing system' [patent_app_type] => 1 [patent_app_number] => 7/876670 [patent_app_country] => US [patent_app_date] => 1992-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6457 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 531 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/504/05504894.pdf [firstpage_image] =>[orig_patent_app_number] => 876670 [rel_patent_id] =>[rel_patent_doc_number] =>)