
Luke S. Wassum
Examiner (ID: 9017, Phone: (571)272-4119 , Office: P/3992 )
| Most Active Art Unit | 3992 |
| Art Unit(s) | 2177, 2859, 2167, 3992 |
| Total Applications | 533 |
| Issued Applications | 324 |
| Pending Applications | 85 |
| Abandoned Applications | 130 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11746538
[patent_doc_number] => 20170200611
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-13
[patent_title] => 'MANUFACTURING METHOD OF MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/182062
[patent_app_country] => US
[patent_app_date] => 2016-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5774
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15182062
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/182062 | MANUFACTURING METHOD OF MEMORY DEVICE | Jun 13, 2016 | Abandoned |
Array
(
[id] => 13695165
[patent_doc_number] => 20170358537
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-14
[patent_title] => METHOD OF WAFER DICING FOR BACKSIDE METALLIZATION
[patent_app_type] => utility
[patent_app_number] => 15/182224
[patent_app_country] => US
[patent_app_date] => 2016-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6442
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15182224
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/182224 | Method of wafer dicing for backside metallization | Jun 13, 2016 | Issued |
Array
(
[id] => 15315303
[patent_doc_number] => 10522365
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-31
[patent_title] => Methods for reducing scratch defects in chemical mechanical planarization
[patent_app_type] => utility
[patent_app_number] => 15/182291
[patent_app_country] => US
[patent_app_date] => 2016-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 16
[patent_no_of_words] => 5505
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15182291
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/182291 | Methods for reducing scratch defects in chemical mechanical planarization | Jun 13, 2016 | Issued |
Array
(
[id] => 16645586
[patent_doc_number] => 10923454
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-16
[patent_title] => Method and apparatus for creating a bond between objects based on formation of inter-diffusion layers
[patent_app_type] => utility
[patent_app_number] => 15/176567
[patent_app_country] => US
[patent_app_date] => 2016-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 35
[patent_no_of_words] => 10486
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15176567
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/176567 | Method and apparatus for creating a bond between objects based on formation of inter-diffusion layers | Jun 7, 2016 | Issued |
Array
(
[id] => 12355083
[patent_doc_number] => 09953873
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-04-24
[patent_title] => Methods of modulating the morphology of epitaxial semiconductor material
[patent_app_type] => utility
[patent_app_number] => 15/163313
[patent_app_country] => US
[patent_app_date] => 2016-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 4427
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 282
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15163313
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/163313 | Methods of modulating the morphology of epitaxial semiconductor material | May 23, 2016 | Issued |
Array
(
[id] => 12061835
[patent_doc_number] => 20170338179
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-23
[patent_title] => 'DEVICE PACKAGE WITH WIRE BOND ASSISTED GROUNDING AND INDUCTORS'
[patent_app_type] => utility
[patent_app_number] => 15/161126
[patent_app_country] => US
[patent_app_date] => 2016-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6733
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15161126
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/161126 | DEVICE PACKAGE WITH WIRE BOND ASSISTED GROUNDING AND INDUCTORS | May 19, 2016 | Abandoned |
Array
(
[id] => 14492049
[patent_doc_number] => 10332825
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-06-25
[patent_title] => Semiconductor package including flip chip mounted IC and vertically integrated inductor
[patent_app_type] => utility
[patent_app_number] => 15/161077
[patent_app_country] => US
[patent_app_date] => 2016-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 4892
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15161077
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/161077 | Semiconductor package including flip chip mounted IC and vertically integrated inductor | May 19, 2016 | Issued |
Array
(
[id] => 11710791
[patent_doc_number] => 20170179290
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-22
[patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 15/161139
[patent_app_country] => US
[patent_app_date] => 2016-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4974
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15161139
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/161139 | Semiconductor device comprising gate structure and doped gate spacer | May 19, 2016 | Issued |
Array
(
[id] => 12061870
[patent_doc_number] => 20170338215
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-23
[patent_title] => 'HETEROGENEOUS CELL ARRAY'
[patent_app_type] => utility
[patent_app_number] => 15/160992
[patent_app_country] => US
[patent_app_date] => 2016-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8403
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15160992
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/160992 | HETEROGENEOUS CELL ARRAY | May 19, 2016 | Abandoned |
Array
(
[id] => 12061993
[patent_doc_number] => 20170338337
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-23
[patent_title] => 'DEVICE STRUCTURE HAVING INTER-DIGITATED BACK TO BACK MOSFETS'
[patent_app_type] => utility
[patent_app_number] => 15/161054
[patent_app_country] => US
[patent_app_date] => 2016-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3419
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15161054
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/161054 | Device structure having inter-digitated back to back MOSFETs | May 19, 2016 | Issued |
Array
(
[id] => 12061938
[patent_doc_number] => 20170338282
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-23
[patent_title] => 'MEMORY MODULE WITH UNPATTERNED STORAGE MATERIAL'
[patent_app_type] => utility
[patent_app_number] => 15/161068
[patent_app_country] => US
[patent_app_date] => 2016-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 12592
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15161068
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/161068 | MEMORY MODULE WITH UNPATTERNED STORAGE MATERIAL | May 19, 2016 | Abandoned |
Array
(
[id] => 11125374
[patent_doc_number] => 20160322348
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-03
[patent_title] => 'METHOD TO MAKE GATE-TO-BODY CONTACT TO RELEASE PLASMA INDUCED CHARGING'
[patent_app_type] => utility
[patent_app_number] => 15/140618
[patent_app_country] => US
[patent_app_date] => 2016-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 3948
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15140618
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/140618 | METHOD TO MAKE GATE-TO-BODY CONTACT TO RELEASE PLASMA INDUCED CHARGING | Apr 27, 2016 | Abandoned |
Array
(
[id] => 11043557
[patent_doc_number] => 20160240514
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-08-18
[patent_title] => 'PACKAGE STRUCTURE AND ITS FABRICATION METHOD'
[patent_app_type] => utility
[patent_app_number] => 15/137416
[patent_app_country] => US
[patent_app_date] => 2016-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6560
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15137416
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/137416 | PACKAGE STRUCTURE AND ITS FABRICATION METHOD | Apr 24, 2016 | Abandoned |
Array
(
[id] => 11710614
[patent_doc_number] => 20170179113
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-22
[patent_title] => 'METHOD FOR FABRICATING A JFET TRANSISTOR WITHIN AN INTEGRATED CIRCUIT AND CORRESPONDING INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 15/133595
[patent_app_country] => US
[patent_app_date] => 2016-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3431
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15133595
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/133595 | Method for fabricating a JFET transistor within an integrated circuit and corresponding integrated circuit | Apr 19, 2016 | Issued |
Array
(
[id] => 17166102
[patent_doc_number] => 11152214
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-10-19
[patent_title] => Structures and methods for equivalent oxide thickness scaling on silicon germanium channel or III-V channel of semiconductor device
[patent_app_type] => utility
[patent_app_number] => 15/133656
[patent_app_country] => US
[patent_app_date] => 2016-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 25
[patent_no_of_words] => 11172
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15133656
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/133656 | Structures and methods for equivalent oxide thickness scaling on silicon germanium channel or III-V channel of semiconductor device | Apr 19, 2016 | Issued |
Array
(
[id] => 11623223
[patent_doc_number] => 20170133411
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-11
[patent_title] => 'FLEXIBLE DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/322142
[patent_app_country] => US
[patent_app_date] => 2016-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1915
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15322142
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/322142 | Method for manufacturing a flexible display device | Mar 28, 2016 | Issued |
Array
(
[id] => 11071521
[patent_doc_number] => 20160268485
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-09-15
[patent_title] => 'METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/054040
[patent_app_country] => US
[patent_app_date] => 2016-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3499
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15054040
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/054040 | Method of manufacturing light-emitting device including sealing materials with phosphor particles | Feb 24, 2016 | Issued |
Array
(
[id] => 14526367
[patent_doc_number] => 10340455
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-07-02
[patent_title] => Manufacturing method of mask plate assembly with colloid
[patent_app_type] => utility
[patent_app_number] => 15/322140
[patent_app_country] => US
[patent_app_date] => 2016-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2636
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15322140
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/322140 | Manufacturing method of mask plate assembly with colloid | Feb 24, 2016 | Issued |
Array
(
[id] => 11061103
[patent_doc_number] => 20160258065
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-09-08
[patent_title] => 'SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD'
[patent_app_type] => utility
[patent_app_number] => 15/051836
[patent_app_country] => US
[patent_app_date] => 2016-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9798
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15051836
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/051836 | Substrate processing method including supplying a fluorine-containing gas on a surface of a substrate | Feb 23, 2016 | Issued |
Array
(
[id] => 11502796
[patent_doc_number] => 20170076982
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-16
[patent_title] => 'DEVICE MANUFACTURING METHOD'
[patent_app_type] => utility
[patent_app_number] => 15/050683
[patent_app_country] => US
[patent_app_date] => 2016-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5997
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15050683
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/050683 | DEVICE MANUFACTURING METHOD | Feb 22, 2016 | Abandoned |