Search

Ly D. Pham

Examiner (ID: 490, Phone: (571)272-1793 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2713, 2818, 2827
Total Applications
2205
Issued Applications
2049
Pending Applications
85
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19820721 [patent_doc_number] => 20250078928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => MEMORY DEVICE, OPERATING METHOD THEREOF, SYSTEM, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/954002 [patent_app_country] => US [patent_app_date] => 2024-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21369 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18954002 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/954002
MEMORY DEVICE, OPERATING METHOD THEREOF, SYSTEM, AND STORAGE MEDIUM Nov 19, 2024 Pending
Array ( [id] => 19820677 [patent_doc_number] => 20250078884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => BUFFER CONFIGURATIONS FOR COMMUNICATIONS BETWEEN MEMORY DIES AND A HOST DEVICE [patent_app_type] => utility [patent_app_number] => 18/948310 [patent_app_country] => US [patent_app_date] => 2024-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16038 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18948310 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/948310
BUFFER CONFIGURATIONS FOR COMMUNICATIONS BETWEEN MEMORY DIES AND A HOST DEVICE Nov 13, 2024 Pending
Array ( [id] => 19803747 [patent_doc_number] => 20250069672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => COLUMN CONTROL CIRCUITS AND STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 18/948283 [patent_app_country] => US [patent_app_date] => 2024-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18948283 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/948283
COLUMN CONTROL CIRCUITS AND STORAGE DEVICES Nov 13, 2024 Pending
Array ( [id] => 20124263 [patent_doc_number] => 20250239294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/937180 [patent_app_country] => US [patent_app_date] => 2024-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1150 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18937180 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/937180
MEMORY DEVICE AND METHOD OF OPERATING THE SAME Nov 4, 2024 Pending
Array ( [id] => 19788254 [patent_doc_number] => 20250061933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => MIDPOINT SENSING REFERENCE GENERATION FOR STT-MRAM [patent_app_type] => utility [patent_app_number] => 18/934463 [patent_app_country] => US [patent_app_date] => 2024-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18934463 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/934463
MIDPOINT SENSING REFERENCE GENERATION FOR STT-MRAM Oct 31, 2024 Pending
Array ( [id] => 20002093 [patent_doc_number] => 20250140315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => Floating Metal Based Flash Memory [patent_app_type] => utility [patent_app_number] => 18/924924 [patent_app_country] => US [patent_app_date] => 2024-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18924924 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/924924
Floating Metal Based Flash Memory Oct 22, 2024 Pending
Array ( [id] => 19757799 [patent_doc_number] => 20250046364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => DATA READ CIRCUIT AND STORAGE DEVICE THEREOF [patent_app_type] => utility [patent_app_number] => 18/923627 [patent_app_country] => US [patent_app_date] => 2024-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13153 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18923627 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/923627
DATA READ CIRCUIT AND STORAGE DEVICE THEREOF Oct 21, 2024 Pending
Array ( [id] => 19726891 [patent_doc_number] => 20250029642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => MATRIX FORMATION FOR PERFORMING COMPUTATIONAL OPERATIONS IN MEMORY [patent_app_type] => utility [patent_app_number] => 18/905537 [patent_app_country] => US [patent_app_date] => 2024-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18905537 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/905537
MATRIX FORMATION FOR PERFORMING COMPUTATIONAL OPERATIONS IN MEMORY Oct 2, 2024 Pending
Array ( [id] => 19695036 [patent_doc_number] => 20250013581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => SEMICONDUCTOR DEVICE WITH SECURE ACCESS KEY AND ASSOCIATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/894594 [patent_app_country] => US [patent_app_date] => 2024-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18894594 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/894594
SEMICONDUCTOR DEVICE WITH SECURE ACCESS KEY AND ASSOCIATED METHODS AND SYSTEMS Sep 23, 2024 Pending
Array ( [id] => 19835469 [patent_doc_number] => 20250087255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => DATA BUFFER FOR MEMORY DEVICES WITH MEMORY ADDRESS REMAPPING [patent_app_type] => utility [patent_app_number] => 18/895130 [patent_app_country] => US [patent_app_date] => 2024-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3928 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18895130 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/895130
DATA BUFFER FOR MEMORY DEVICES WITH MEMORY ADDRESS REMAPPING Sep 23, 2024 Pending
Array ( [id] => 20324349 [patent_doc_number] => 20250336437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/891289 [patent_app_country] => US [patent_app_date] => 2024-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14426 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18891289 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/891289
MEMORY DEVICE Sep 19, 2024 Pending
Array ( [id] => 19696096 [patent_doc_number] => 20250014641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => MULTI-STEP PRE-READ FOR WRITE OPERATIONS IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/890624 [patent_app_country] => US [patent_app_date] => 2024-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10068 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18890624 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/890624
MULTI-STEP PRE-READ FOR WRITE OPERATIONS IN MEMORY DEVICES Sep 18, 2024 Pending
Array ( [id] => 19696089 [patent_doc_number] => 20250014634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => SEMICONDUCTOR MEMORY DEVICES AND ELECTRONIC DEVICES INCLUDING THE SEMICONDUCTOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/887410 [patent_app_country] => US [patent_app_date] => 2024-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14071 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18887410 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/887410
SEMICONDUCTOR MEMORY DEVICES AND ELECTRONIC DEVICES INCLUDING THE SEMICONDUCTOR MEMORY DEVICES Sep 16, 2024 Pending
Array ( [id] => 20602951 [patent_doc_number] => 20260080963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-19 [patent_title] => HYBRID TEST READ SCHEME USING IN-NAND PARTIAL CHECKSUM [patent_app_type] => utility [patent_app_number] => 18/884842 [patent_app_country] => US [patent_app_date] => 2024-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18884842 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/884842
HYBRID TEST READ SCHEME USING IN-NAND PARTIAL CHECKSUM Sep 12, 2024 Pending
Array ( [id] => 20588398 [patent_doc_number] => 20260073994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-12 [patent_title] => GATE INDUCED DRAIN LEAKAGE ERASE WITH ADAPTIVE BIAS ON TOP DRAINSIDE SELECT GATE TRANSISTOR AND BOTTOM SOURCE-SIDE SELECT GATE TRANSISTOR [patent_app_type] => utility [patent_app_number] => 18/883219 [patent_app_country] => US [patent_app_date] => 2024-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15438 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18883219 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/883219
GATE INDUCED DRAIN LEAKAGE ERASE WITH ADAPTIVE BIAS ON TOP DRAINSIDE SELECT GATE TRANSISTOR AND BOTTOM SOURCE-SIDE SELECT GATE TRANSISTOR Sep 11, 2024 Pending
Array ( [id] => 20250874 [patent_doc_number] => 20250299743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/883316 [patent_app_country] => US [patent_app_date] => 2024-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12854 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18883316 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/883316
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM Sep 11, 2024 Pending
Array ( [id] => 20019283 [patent_doc_number] => 20250157505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => NONVOLATILE MEMORY DEVICE, METHOD OF CONTROLLING INITIALIZATION OF NONVOLATILE MEMORY DEVICE, AND STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/825025 [patent_app_country] => US [patent_app_date] => 2024-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3414 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18825025 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/825025
NONVOLATILE MEMORY DEVICE, METHOD OF CONTROLLING INITIALIZATION OF NONVOLATILE MEMORY DEVICE, AND STORAGE DEVICE Sep 4, 2024 Pending
Array ( [id] => 20096094 [patent_doc_number] => 20250226030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => SEMICONDUCTOR MEMORY DEVICE INCLUDING MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/818882 [patent_app_country] => US [patent_app_date] => 2024-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8228 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18818882 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/818882
SEMICONDUCTOR MEMORY DEVICE INCLUDING MEMORY CELLS Aug 28, 2024 Pending
Array ( [id] => 20558165 [patent_doc_number] => 20260057951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-26 [patent_title] => MEMORY DEVICE AND INTERNAL VOLTAGE MEASURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/815802 [patent_app_country] => US [patent_app_date] => 2024-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18815802 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/815802
Memory device and internal voltage measuring method thereof Aug 25, 2024 Issued
Array ( [id] => 19618905 [patent_doc_number] => 20240404585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => Memory Device Comprising Electrically Floating Body Transistor [patent_app_type] => utility [patent_app_number] => 18/803630 [patent_app_country] => US [patent_app_date] => 2024-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18803630 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/803630
Memory Device Comprising Electrically Floating Body Transistor Aug 12, 2024 Pending
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