Search

Ly D. Pham

Examiner (ID: 15722)

Most Active Art Unit
2827
Art Unit(s)
2827, 2818, 2713
Total Applications
2164
Issued Applications
2016
Pending Applications
83
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17645046 [patent_doc_number] => 20220172785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => OPERATION METHOD OF CONTROLLER CONFIGURED TO CONTROL NONVOLATILE MEMORY DEVICE AND OPERATION METHOD OF STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/534989 [patent_app_country] => US [patent_app_date] => 2021-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17534989 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/534989
Operation method of controller configured to control nonvolatile memory device and operation method of storage device Nov 23, 2021 Issued
Array ( [id] => 18912862 [patent_doc_number] => 11875846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Optimization of soft bit windows based on signal and noise characteristics of memory cells [patent_app_type] => utility [patent_app_number] => 17/534907 [patent_app_country] => US [patent_app_date] => 2021-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 14076 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17534907 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/534907
Optimization of soft bit windows based on signal and noise characteristics of memory cells Nov 23, 2021 Issued
Array ( [id] => 18848523 [patent_doc_number] => 20230410927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => MAGNONIC ACTIVE RING MEMORY AND LOGIC [patent_app_type] => utility [patent_app_number] => 18/037951 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18037951 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/037951
Magnonic active ring memory and logic Nov 21, 2021 Issued
Array ( [id] => 18607857 [patent_doc_number] => 11749333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 17/531424 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3977 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531424 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/531424
Memory system Nov 18, 2021 Issued
Array ( [id] => 17565243 [patent_doc_number] => 20220129392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => SEMICONDUCTOR DEVICE WITH SECURE ACCESS KEY AND ASSOCIATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/530461 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530461 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/530461
Semiconductor device with secure access key and associated methods and systems Nov 18, 2021 Issued
Array ( [id] => 18379415 [patent_doc_number] => 20230154504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => MLM MAPPED NAND LATCH [patent_app_type] => utility [patent_app_number] => 17/455007 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455007 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/455007
MLM mapped NAND latch Nov 14, 2021 Issued
Array ( [id] => 18606521 [patent_doc_number] => 11747985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Memory system, integrated circuit system, and operation method of memory system [patent_app_type] => utility [patent_app_number] => 17/507442 [patent_app_country] => US [patent_app_date] => 2021-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10570 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17507442 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/507442
Memory system, integrated circuit system, and operation method of memory system Oct 20, 2021 Issued
Array ( [id] => 18639294 [patent_doc_number] => 11763910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Multi-command memory accesses [patent_app_type] => utility [patent_app_number] => 17/506421 [patent_app_country] => US [patent_app_date] => 2021-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 14521 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17506421 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/506421
Multi-command memory accesses Oct 19, 2021 Issued
Array ( [id] => 18639270 [patent_doc_number] => 11763886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Techniques to access a self-selecting memory device [patent_app_type] => utility [patent_app_number] => 17/499290 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 18130 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17499290 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/499290
Techniques to access a self-selecting memory device Oct 11, 2021 Issued
Array ( [id] => 17338166 [patent_doc_number] => 20220004497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => APPARATUSES AND METHODS FOR CACHE OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/479853 [patent_app_country] => US [patent_app_date] => 2021-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25125 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17479853 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/479853
Apparatuses and methods for cache operations Sep 19, 2021 Issued
Array ( [id] => 18356804 [patent_doc_number] => 11645206 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Distributed memory-augmented neural network architecture [patent_app_type] => utility [patent_app_number] => 17/472764 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7671 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17472764 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/472764
Distributed memory-augmented neural network architecture Sep 12, 2021 Issued
Array ( [id] => 18668546 [patent_doc_number] => 11775446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Methods and apparatus to facilitate atomic compare and swap in cache for a coherent level 1 data cache system [patent_app_type] => utility [patent_app_number] => 17/472811 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 54 [patent_no_of_words] => 95336 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17472811 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/472811
Methods and apparatus to facilitate atomic compare and swap in cache for a coherent level 1 data cache system Sep 12, 2021 Issued
Array ( [id] => 18008208 [patent_doc_number] => 20220366975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => GAUSSIAN SAMPLING APPARATUS AND METHOD BASED ON RESISTIVE RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 17/458129 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3362 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458129 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/458129
Gaussian sampling apparatus and method based on resistive random access memory Aug 25, 2021 Issued
Array ( [id] => 17477116 [patent_doc_number] => 20220084620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => FAIL BIT REPAIR SOLUTION DETERMINATION METHOD AND DEVICE [patent_app_type] => utility [patent_app_number] => 17/412372 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412372 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412372
Fail bit repair solution determination method and device Aug 25, 2021 Issued
Array ( [id] => 18751320 [patent_doc_number] => 11810638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Memory device including multiple memory chips and data signal lines and a method of operating the memory device [patent_app_type] => utility [patent_app_number] => 17/410210 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10078 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17410210 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/410210
Memory device including multiple memory chips and data signal lines and a method of operating the memory device Aug 23, 2021 Issued
Array ( [id] => 18704444 [patent_doc_number] => 11790960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Data transmission circuit, method and storage device [patent_app_type] => utility [patent_app_number] => 17/626794 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5179 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17626794 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/626794
Data transmission circuit, method and storage device Aug 17, 2021 Issued
Array ( [id] => 18196293 [patent_doc_number] => 20230049812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => SPIN-ORBIT-TORQUE MAGNETORESISTIVE RANDOM-ACCESS MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 17/401394 [patent_app_country] => US [patent_app_date] => 2021-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6564 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17401394 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/401394
Spin-orbit-torque magnetoresistive random-access memory array Aug 12, 2021 Issued
Array ( [id] => 18766756 [patent_doc_number] => 11817163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Circuit for detecting state of anti-fuse storage unit and memory device thereof [patent_app_type] => utility [patent_app_number] => 17/400517 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8156 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17400517 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/400517
Circuit for detecting state of anti-fuse storage unit and memory device thereof Aug 11, 2021 Issued
Array ( [id] => 17389094 [patent_doc_number] => 20220036946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => MULTI-LEVEL SELF-SELECTING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/399853 [patent_app_country] => US [patent_app_date] => 2021-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20198 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399853 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/399853
Multi-level self-selecting memory device Aug 10, 2021 Issued
Array ( [id] => 17218820 [patent_doc_number] => 20210352158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => Redundancy In A Network Centric Process Control System [patent_app_type] => utility [patent_app_number] => 17/384100 [patent_app_country] => US [patent_app_date] => 2021-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17384100 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/384100
Redundancy in a network centric process control system Jul 22, 2021 Issued
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