Search

Ly D. Pham

Examiner (ID: 15722)

Most Active Art Unit
2827
Art Unit(s)
2827, 2818, 2713
Total Applications
2164
Issued Applications
2016
Pending Applications
83
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17100160 [patent_doc_number] => 20210287951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => SEMICONDUCTOR CHIPS INCLUDING THROUGH ELECTRODES AND METHODS OF TESTING THE THROUGH ELECTRODES [patent_app_type] => utility [patent_app_number] => 17/334399 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17334399 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/334399
Semiconductor chips including through electrodes and methods of testing the through electrodes May 27, 2021 Issued
Array ( [id] => 17039712 [patent_doc_number] => 20210256348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => AUTOMATED METHODS FOR CONVERSIONS TO A LOWER PRECISION DATA FORMAT [patent_app_type] => utility [patent_app_number] => 17/306171 [patent_app_country] => US [patent_app_date] => 2021-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17306171 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/306171
AUTOMATED METHODS FOR CONVERSIONS TO A LOWER PRECISION DATA FORMAT May 2, 2021 Pending
Array ( [id] => 17173806 [patent_doc_number] => 20210327477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => LOW STANDBY POWER WITH FAST TURN ON METHOD FOR NON-VOLATILE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/245804 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17245804 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/245804
Low standby power with fast turn on method for non-volatile memory devices Apr 29, 2021 Issued
Array ( [id] => 17024056 [patent_doc_number] => 20210247927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => WRITE OPERATION CIRCUIT, SEMICONDUCTOR MEMORY AND WRITE OPERATION METHOD [patent_app_type] => utility [patent_app_number] => 17/242281 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6093 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242281 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/242281
Write operation circuit, semiconductor memory and write operation method Apr 26, 2021 Issued
Array ( [id] => 17723162 [patent_doc_number] => 20220215884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => DYNAMIC RANDOM ACCESS MEMORY AND PROGRAMMING METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 17/240008 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17240008 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/240008
Dynamic random access memory and programming method therefor Apr 25, 2021 Issued
Array ( [id] => 16993785 [patent_doc_number] => 20210232205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => REDUCING POWER CONSUMPTION IN A NEURAL NETWORK ENVIRONMENT USING DATA MANAGEMENT [patent_app_type] => utility [patent_app_number] => 17/233379 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17233379 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/233379
Reducing power consumption in a neural network environment using data management Apr 15, 2021 Issued
Array ( [id] => 16993007 [patent_doc_number] => 20210231427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => INFORMATION PROCESSING APPARATUS, NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM HAVING STORED THEREIN INFORMATION PROCESSING PROGRAM, INFORMATION PROCESSING SYSTEM, AND INFORMATION PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 17/231109 [patent_app_country] => US [patent_app_date] => 2021-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16665 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17231109 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/231109
Information processing apparatus, non-transitory computer-readable storage medium having stored therein information processing program, information processing system, and information processing method Apr 14, 2021 Issued
Array ( [id] => 18371644 [patent_doc_number] => 11651825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Random value generator [patent_app_type] => utility [patent_app_number] => 17/227977 [patent_app_country] => US [patent_app_date] => 2021-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 15003 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17227977 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/227977
Random value generator Apr 11, 2021 Issued
Array ( [id] => 17917227 [patent_doc_number] => 20220319623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => ECC BUFFER REDUCTION IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/223375 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223375 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/223375
ECC buffer reduction in a memory device Apr 5, 2021 Issued
Array ( [id] => 16981187 [patent_doc_number] => 20210225424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => NONVOLATILE SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/222969 [patent_app_country] => US [patent_app_date] => 2021-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17222969 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/222969
Nonvolatile semiconductor memory device Apr 4, 2021 Issued
Array ( [id] => 17917226 [patent_doc_number] => 20220319622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => REMAPPING BAD BLOCKS IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/218385 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8011 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17218385 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/218385
Remapping bad blocks in a memory sub-system Mar 30, 2021 Issued
Array ( [id] => 18292163 [patent_doc_number] => 11621036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-04 [patent_title] => Method of operating an integrated circuit and integrated circuit [patent_app_type] => utility [patent_app_number] => 17/217215 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 17476 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17217215 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/217215
Method of operating an integrated circuit and integrated circuit Mar 29, 2021 Issued
Array ( [id] => 17040749 [patent_doc_number] => 20210257385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells And Operative Through-Array-Vias [patent_app_type] => utility [patent_app_number] => 17/215308 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7198 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17215308 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/215308
Memory arrays and methods used in forming a memory array comprising strings of memory cells and operative through-array-vias Mar 28, 2021 Issued
Array ( [id] => 18331887 [patent_doc_number] => 11637145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Multi-component cell architectures for a memory device [patent_app_type] => utility [patent_app_number] => 17/210571 [patent_app_country] => US [patent_app_date] => 2021-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 15055 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17210571 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/210571
Multi-component cell architectures for a memory device Mar 23, 2021 Issued
Array ( [id] => 17900482 [patent_doc_number] => 20220310144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => Wordline Driver Architecture [patent_app_type] => utility [patent_app_number] => 17/209876 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17209876 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/209876
Wordline driver architecture Mar 22, 2021 Issued
Array ( [id] => 17373401 [patent_doc_number] => 20220028453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => MEMORY CIRCUIT AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/209965 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17209965 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/209965
Memory circuit and method of operating the same Mar 22, 2021 Issued
Array ( [id] => 19626212 [patent_doc_number] => 12165046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Enabling hierarchical data loading in a resistive processing unit (RPU) array for reduced communication cost [patent_app_type] => utility [patent_app_number] => 17/203705 [patent_app_country] => US [patent_app_date] => 2021-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8109 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17203705 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/203705
Enabling hierarchical data loading in a resistive processing unit (RPU) array for reduced communication cost Mar 15, 2021 Issued
Array ( [id] => 18874457 [patent_doc_number] => 11862278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Memory test systems and memory test methods [patent_app_type] => utility [patent_app_number] => 17/433354 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7234 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17433354 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/433354
Memory test systems and memory test methods Mar 11, 2021 Issued
Array ( [id] => 17893065 [patent_doc_number] => 11456044 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-27 [patent_title] => Reverse VT-state operation and optimized BiCS device structure [patent_app_type] => utility [patent_app_number] => 17/199245 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 13914 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199245 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199245
Reverse VT-state operation and optimized BiCS device structure Mar 10, 2021 Issued
Array ( [id] => 17925697 [patent_doc_number] => 11468957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Architecture and method for NAND memory operation [patent_app_type] => utility [patent_app_number] => 17/191768 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10529 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17191768 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/191768
Architecture and method for NAND memory operation Mar 3, 2021 Issued
Menu