Search

Ly D. Pham

Examiner (ID: 15722)

Most Active Art Unit
2827
Art Unit(s)
2827, 2818, 2713
Total Applications
2164
Issued Applications
2016
Pending Applications
83
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17854928 [patent_doc_number] => 20220284971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => APPLICATION BASED VERIFY LEVEL OFFSETS FOR NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/192090 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17588 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192090 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/192090
Application based verify level offsets for non-volatile memory Mar 3, 2021 Issued
Array ( [id] => 17855338 [patent_doc_number] => 20220285381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => SEMI-CONDUCTOR DEVICE HAVING DOUBLE-GATE AND METHOD FOR SETTING SYNAPSE WEIGHT OF TARGET SEMI-CONDUCTOR DEVICE WITHIN NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 17/189574 [patent_app_country] => US [patent_app_date] => 2021-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8665 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17189574 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/189574
Semi-conductor device having double-gate and method for setting synapse weight of target semi-conductor device within neural network Mar 1, 2021 Issued
Array ( [id] => 16936115 [patent_doc_number] => 20210202004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => REDUNDANCY IN MICROELECTRONIC DEVICES, AND RELATED METHODS, DEVICES, AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/249284 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17249284 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/249284
Redundancy in microelectronic devices, and related methods, devices, and systems Feb 24, 2021 Issued
Array ( [id] => 17833375 [patent_doc_number] => 20220270679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => READ CACHE FOR RESET READ DISTURB MITIGATION [patent_app_type] => utility [patent_app_number] => 17/181346 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5124 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181346 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/181346
Read cache for reset read disturb mitigation Feb 21, 2021 Issued
Array ( [id] => 17025214 [patent_doc_number] => 20210249086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => EEPROM MEMORY DEVICE AND CORRESPONDING METHOD [patent_app_type] => utility [patent_app_number] => 17/166107 [patent_app_country] => US [patent_app_date] => 2021-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8266 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17166107 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/166107
EEPROM memory device and corresponding method Feb 2, 2021 Issued
Array ( [id] => 17025226 [patent_doc_number] => 20210249098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => MEMORY CONTROLLER AND FLASH MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/161878 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161878 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/161878
Memory controller and flash memory system Jan 28, 2021 Issued
Array ( [id] => 17402642 [patent_doc_number] => 20220044733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/161197 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11971 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161197 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/161197
Semiconductor memory device and method of operating the same Jan 27, 2021 Issued
Array ( [id] => 16904516 [patent_doc_number] => 20210183432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/161403 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161403 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/161403
Memory device comprising electrically floating body transistor Jan 27, 2021 Issued
Array ( [id] => 17683223 [patent_doc_number] => 11367484 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-21 [patent_title] => Multi-step pre-read for write operations in memory devices [patent_app_type] => utility [patent_app_number] => 17/154644 [patent_app_country] => US [patent_app_date] => 2021-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10000 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17154644 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/154644
Multi-step pre-read for write operations in memory devices Jan 20, 2021 Issued
Array ( [id] => 16811791 [patent_doc_number] => 20210134346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => REDUNDANT VOLTAGE REGULATOR FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/150514 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9455 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150514 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150514
Redundant voltage regulator for memory devices Jan 14, 2021 Issued
Array ( [id] => 17737752 [patent_doc_number] => 20220223214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => MEMORY APPARATUS AND METHOD OF OPERATION USING PLANE DEPENDENT RAMP RATE AND TIMING CONTROL FOR PROGRAM OPERATION [patent_app_type] => utility [patent_app_number] => 17/149136 [patent_app_country] => US [patent_app_date] => 2021-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20046 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17149136 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/149136
Memory apparatus and method of operation using plane dependent ramp rate and timing control for program operation Jan 13, 2021 Issued
Array ( [id] => 18292160 [patent_doc_number] => 11621033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-04 [patent_title] => Techniques for low power operation [patent_app_type] => utility [patent_app_number] => 17/145066 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 13204 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145066 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/145066
Techniques for low power operation Jan 7, 2021 Issued
Array ( [id] => 18236201 [patent_doc_number] => 11600769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => High density spin orbit torque magnetic random access memory [patent_app_type] => utility [patent_app_number] => 17/145126 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4971 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145126 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/145126
High density spin orbit torque magnetic random access memory Jan 7, 2021 Issued
Array ( [id] => 16872667 [patent_doc_number] => 20210166134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => Home Wireless Discovery [patent_app_type] => utility [patent_app_number] => 17/135596 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12914 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135596 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135596
Home wireless discovery Dec 27, 2020 Issued
Array ( [id] => 17438729 [patent_doc_number] => 11264069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Apparatus with a calibration mechanism [patent_app_type] => utility [patent_app_number] => 17/131156 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 9328 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17131156 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/131156
Apparatus with a calibration mechanism Dec 21, 2020 Issued
Array ( [id] => 17144976 [patent_doc_number] => 20210312989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => NONVOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/126933 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17126933 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/126933
Nonvolatile memory device and operation method thereof Dec 17, 2020 Issued
Array ( [id] => 17691853 [patent_doc_number] => 20220199146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => APPARATUSES AND METHODS FOR INPUT BUFFER POWER SAVINGS [patent_app_type] => utility [patent_app_number] => 17/125095 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125095 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125095
Apparatuses and methods for input buffer power savings Dec 16, 2020 Issued
Array ( [id] => 17529682 [patent_doc_number] => 11302380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Memory controller device and phase calibration method [patent_app_type] => utility [patent_app_number] => 17/120344 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5329 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120344 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120344
Memory controller device and phase calibration method Dec 13, 2020 Issued
Array ( [id] => 17925703 [patent_doc_number] => 11468963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Memory device and read method thereof [patent_app_type] => utility [patent_app_number] => 17/115412 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4602 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115412 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115412
Memory device and read method thereof Dec 7, 2020 Issued
Array ( [id] => 16781428 [patent_doc_number] => 20210118507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => LAYOUT PATTERN OF TWO-PORT TERNARY CONTENT ADDRESSABLE MEMORY [patent_app_type] => utility [patent_app_number] => 17/114373 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114373 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114373
Layout pattern of two-port ternary content addressable memory Dec 6, 2020 Issued
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