Search

Ly D. Pham

Examiner (ID: 15722)

Most Active Art Unit
2827
Art Unit(s)
2827, 2818, 2713
Total Applications
2164
Issued Applications
2016
Pending Applications
83
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16723493 [patent_doc_number] => 20210090640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => CIRCUIT FOR REDUCING LEAKAGE CURRENT OF SRAM MEMORY ARRAY AND CONTROL METHOD FOR SAME [patent_app_type] => utility [patent_app_number] => 17/111379 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111379 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/111379
Circuit for reducing leakage current of SRAM memory array and control method for same Dec 2, 2020 Issued
Array ( [id] => 17353003 [patent_doc_number] => 11227647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/106242 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7997 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106242 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/106242
Semiconductor device Nov 29, 2020 Issued
Array ( [id] => 17683219 [patent_doc_number] => 11367480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Memory device implementing multiple port read [patent_app_type] => utility [patent_app_number] => 17/104953 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3478 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104953 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/104953
Memory device implementing multiple port read Nov 24, 2020 Issued
Array ( [id] => 17485666 [patent_doc_number] => 20220093170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => DUAL-PORT SRAM CELL AND LAYOUT STRUCTURE THEREOF [patent_app_type] => utility [patent_app_number] => 17/098186 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5973 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17098186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/098186
Dual-port SRAM cell and layout structure thereof Nov 12, 2020 Issued
Array ( [id] => 17636928 [patent_doc_number] => 11347652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Banked memory architecture for multiple parallel datapath channels in an accelerator [patent_app_type] => utility [patent_app_number] => 17/097205 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11171 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097205 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/097205
Banked memory architecture for multiple parallel datapath channels in an accelerator Nov 12, 2020 Issued
Array ( [id] => 17956160 [patent_doc_number] => 11482273 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-25 [patent_title] => Strobe tree circuit for capturing data using a memory-sourced strobe [patent_app_type] => utility [patent_app_number] => 17/095592 [patent_app_country] => US [patent_app_date] => 2020-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 8049 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17095592 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/095592
Strobe tree circuit for capturing data using a memory-sourced strobe Nov 10, 2020 Issued
Array ( [id] => 17283918 [patent_doc_number] => 11200958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Memories for mitigating program disturb [patent_app_type] => utility [patent_app_number] => 17/091379 [patent_app_country] => US [patent_app_date] => 2020-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10786 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17091379 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/091379
Memories for mitigating program disturb Nov 5, 2020 Issued
Array ( [id] => 18155936 [patent_doc_number] => 11568925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 17/084880 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 9599 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17084880 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/084880
Memory device Oct 29, 2020 Issued
Array ( [id] => 16622662 [patent_doc_number] => 20210041315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => Waist Measuring Belt [patent_app_type] => utility [patent_app_number] => 17/081822 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12019 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081822 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/081822
Waist measuring belt Oct 26, 2020 Issued
Array ( [id] => 17159613 [patent_doc_number] => 20210320664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING DELAY COMPENSATION CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/077891 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12884 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17077891 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/077891
Semiconductor device including delay compensation circuit Oct 21, 2020 Issued
Array ( [id] => 16624586 [patent_doc_number] => 20210043239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => MEMORY CIRCUIT AND METHOD OF OPERATING SAME [patent_app_type] => utility [patent_app_number] => 17/076965 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10207 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17076965 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/076965
Memory circuit and method of operating same Oct 21, 2020 Issued
Array ( [id] => 18138628 [patent_doc_number] => 11564331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Electronic device with a card-level thermal regulator mechanism and associated systems, devices, and methods [patent_app_type] => utility [patent_app_number] => 17/075643 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6344 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075643 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/075643
Electronic device with a card-level thermal regulator mechanism and associated systems, devices, and methods Oct 19, 2020 Issued
Array ( [id] => 17971117 [patent_doc_number] => 11488664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Distributing device array currents across segment mirrors [patent_app_type] => utility [patent_app_number] => 17/068852 [patent_app_country] => US [patent_app_date] => 2020-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7812 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068852 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/068852
Distributing device array currents across segment mirrors Oct 12, 2020 Issued
Array ( [id] => 17395703 [patent_doc_number] => 11244724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Content addressable memory device [patent_app_type] => utility [patent_app_number] => 17/063734 [patent_app_country] => US [patent_app_date] => 2020-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5948 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17063734 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/063734
Content addressable memory device Oct 5, 2020 Issued
Array ( [id] => 17424071 [patent_doc_number] => 11257532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Apparatuses and methods for controlling word line discharge [patent_app_type] => utility [patent_app_number] => 17/038604 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10544 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17038604 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/038604
Apparatuses and methods for controlling word line discharge Sep 29, 2020 Issued
Array ( [id] => 16560124 [patent_doc_number] => 20210005273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => CONTROLLER AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/026655 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17026655 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/026655
Controller and method of operating the same Sep 20, 2020 Issued
Array ( [id] => 18016151 [patent_doc_number] => 11508454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Data storage device and method of operating the same [patent_app_type] => utility [patent_app_number] => 17/025765 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13067 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17025765 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/025765
Data storage device and method of operating the same Sep 17, 2020 Issued
Array ( [id] => 16723500 [patent_doc_number] => 20210090647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/022580 [patent_app_country] => US [patent_app_date] => 2020-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17022580 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/022580
Memory device Sep 15, 2020 Issued
Array ( [id] => 16723531 [patent_doc_number] => 20210090678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => MEMORY CONTROLLERS, STORAGE DEVICES, AND OPERATING METHODS OF THE STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 17/019929 [patent_app_country] => US [patent_app_date] => 2020-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14832 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17019929 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/019929
Memory controllers, storage devices, and operating methods of the storage devices Sep 13, 2020 Issued
Array ( [id] => 17318534 [patent_doc_number] => 20210407584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => POWER GATING CONTROL CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE POWER GATING CONTROL CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/020206 [patent_app_country] => US [patent_app_date] => 2020-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9179 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17020206 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/020206
Power gating control circuit and semiconductor apparatus including the power gating control circuit Sep 13, 2020 Issued
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